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TMP1962F10AXBG tmp1962f-1 32-bit risc microprocessor tx19 family TMP1962F10AXBG 1. features the tx19 is a family of high-performance 32-bit micr oprocessors that offers the speed of a 32-bit risc solution with the added advantage of a significantly reduce d code size of a 16-bit archit ecture. the instruction set of the tx19 includes as a subset the 32-bit instructions of the tx39, which is based on the mips r3000a tm architecture. additionally, the tx19 supports the mips16 ap plication-specific extensions (ase) for improved code density. the tmp1962 is built on a tx19 core processor and a selection of intelligent peripherals. the tmp1962 is suitable for low-voltage and low-power applications. features of the tmp1962 include the following: (1) tx19 core processor 1) two instruction set architecture (isa) modes: 16-bit isa for code density and 32-bit isa for speed ? the 16-bit isa is object-code compatible with the code-efficient mips16 ase. ? the 32-bit isa is object-cod e compatible with the hi gh-performance tx39 family. 2) high performance combined with low power consumption ? high performance ? single clock cycle execution for most instructions ? 3-operand computational instructions for high instruction throughput ? 5-stage pipeline ? on-chip high-speed memory ? dsp function: executes 32-bit x 32-bit multiplier operations in a single clock cycle. ? the information contained herein is subject to change without notice. ? the information contained herein is present ed only as a guide for the applications of our products. no responsibility is assume d by toshiba for any infringements of patents or other rights of the th ird parties which may result from its use. no license is gran ted by implication or otherwise under any patent or patent rights of toshiba or others. ? toshiba is continually working to improve the quality and reli ability of its products. neverthel ess, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vul nerability to physical stress. it is the re sponsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire syste m, and to avoid situations in which a malfuncti on or failure of such toshiba products could cause loss of human life, bodily inju ry or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specificati ons. also, please keep in mind the precauti ons and conditions set forth in the ?handlin g guide for semiconductor devices,? or ?toshi ba semiconductor reliabi lity handbook? etc.. ? the toshiba products listed in this document are intended fo r usage in general electronics appl ications (computer, personal equipment, office equipment, measuring equipm ent, industrial robotics, domestic applianc es, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requi res extraordinarily high quality and/or reliability or a malfun ctionor failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, tr affic signal instruments, combustion con trol instruments, medical instruments, all types of safety devices , etc.. unintended usage of toshiba products listed in this docume nt shall be made at the customer?s own risk. ? the products described in this document are subj ect to the foreign exchange and foreign trade laws. ? toshiba products should not be embedded to the downstream pro ducts which are prohibited to be produced and sold, under any law and regulations. ? for a discussion of how the reliability of microcontrollers can be predicted, please refer to section 1.3 of the chapter entitl ed quality and reliability assurance/handling precautions. 030619ebp
TMP1962F10AXBG tmp1962f-2 ? low power consumption ? optimized design using a low-power cell library ? programmable standby modes in which processor clocks are stopped 3) fast interrupt response suitable for real-time control ? distinct starting locations for each interrupt service routine ? automatically generated vector s for each interrupt source ? automatic updates of the interrupt mask level (2) on-chip rom/ram product on-chip rom on-chip ram tmp1962c10bxbg 1 mbyte 40 kbyte TMP1962F10AXBG 1 mbyte (flash) 40 kbyte collection function on rom (8 words x 8 blocks) (3) external memory expansion ? 16-mbyte off-chip address space for code and data ? external bus interface with dynamic bus sizing for 8-bit and 16-bit data ports (separate bus/multiplex bus) (4) 8-channel dma controller ? interrupt- or software-triggered ? dma transfers between on-chip or external memory and i/o module (5) 12-channel 8-bit timer ? 8-bit/16-bit/24-bit/32-bit interval timer mode ? 8-bit pwm mode ? 8-bit ppg mode (6) 4-channel 16-bit timer ? 16-bit interval timer mode ? 16-bit event counter mode ? 16-bit ppg output ? input capture function ? 2-channel dual input counter function (7) 32-bit input capture ? 8-channel 32-bit input capture register ? 8-channel 32-bit compare register ? 1-channel 32-bit time base timer (8) 7-channel general-purpose serial interface either uart mode or synchronous transfer mode can be selected. (9) 1-channel serial bus interface either i 2 c bus mode or clock-synchronous mode can be selected. (10) 24-channel 10-bit a/d converter (with internal sample/hold)
TMP1962F10AXBG tmp1962f-3 ? external trigger start function ? fixed channel/scan mode ? single/repeat mode ? timer monitor function (11) watchdog timer (12) 4-channel chip select/wait controller (13) interrupt sources ? 4 cpu interrupts: software interrupt instruction ? 55 internal interrupts: 7 priority levels, with the exception of the watchdog timer interrupt ? 25 external interrupts: 7 priority levels, with the exception of the nmi interrupt 1 used for an interrupt source and 14 used for kwup (14) 202-pin input/output ports (15) four standby modes ? idle (halt, doze), stop (16) clock generator ? on-chip pll (x3) ? clock gear: divides the operating speed of the cpu by 1/2, 1/4 or 1/8
TMP1962F10AXBG tmp1962f-4 (17) endian ......... bi-endian big-endian higher address 31 24 23 16 15 8 7 0 word address 8 9 10 11 8 4 5 6 7 4 0 1 2 3 0 lower address byte 0 is the most significant byte (msb) (bits 31-24) the address of a word data item is the address of its msb (byte 0). little-endian higher address 31 24 23 16 15 8 7 0 word address 11 10 9 8 8 7 6 5 4 4 3 2 1 0 0 lower address byte 0 is the least significant byte (lsb) (bits 7-0) the address of a word data item is the address of its lsb (byte 0). (18) operating frequency 40.5 mhz (vcc = 2.2 v to 2.7 v) (19) package p-fbga281 (13 x 13 x 0.65 mm pitch)
TMP1962F10AXBG tmp1962f-5 figure 1.1 TMP1962F10AXBG block diagram tx19 processor core tx19 cpu mac dsu 1 mbyte flash rom 40 kbyte ram rom correction dmac (8ch) cg intc ebif i/o bus i/f 8-bit tmra 0/1 to a/b (12ch) 16-bit tmrb 0 to 3 (4ch) 32-bit tmrc tbt (1ch) 32-bit tmrc input capture 0 to 7 (8ch) 32-bit tmrc compare 0 to 7 (8ch) 10-bit adc (24ch) sio 0 to 6 (7ch) i 2 c (1ch) port0 to port6 (shared with external bus i/f) wdt kwup 0 to d (14ch) port7 to port9 (shared with adc input) porta to portl, portn (shared with function pins) portm, porto to portp (general port)
TMP1962F10AXBG tmp1962f-6 2. pin assignment this section contains pin assignments for the TMP1962F10AXBG as well as brief description of the TMP1962F10AXBG input and output signals. 2.1 pin assignment the following illustrates the TMP1962F10AXBG pin assignment. figure 2.1 pin assignment (p-fbga281) the following provides a pin cross reference by pin number. table 2.1 pin cross reference by pin number (1/2) pin no. pin name pin no. pin name pin no. pin name pin no. pin name pin no. pin name a1 nc a13 pk1/key1 b8 p75/ain5 c2 pcst3 (dsu) c14 pk6/key6 a2 vrefl a14 pi1/int1 b9 pl0/ta4in c3 p92/ain18 c15 pi5/int9 a3 p90/ain16 a15 pi3/int3 b10 pl3/taain c4 p95/ain21 c16 tck (jtag) a4 p93/ain19 a16 pi6/inta b11 pm1 c5 p82/ain10 c17 cvcc2 a5 p80/ain8 a17 x2 b12 pm4 c6 p85/ain13 c18 xt2 a6 p83/ain11 b1 avcc31 b13 pk2/key2 c7 p72/ain2 d1 sdao/tpc (dsu) a7 p70/ain0 b2 vrefh b14 pi2/int2 c8 avss d2 pcst2 (dsu) a8 p74/ain4 b3 p91/ain17 b15 pi4/int4 c9 pl1/ta6in d3 sdi/ dint (dsu) a9 nc b4 p94/ain20 b16 pi7 c10 pl4/tb0in0 d4 dvcc2 a10 pl2/ta8in b5 p81/ain9 b17 cvss c11 pm2 d5 p96/ain22 a11 pm0 b6 p84/ain12 b18 x1 c12 pm5 d6 p86/ain14 a12 pk0/key0 b7 p71/ain1 c1 pcst0 (dsu) c13 pk3/key3 d7 p73/ain3 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 a 17 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 e1 e2 e3 e4 e5 e6 e7 e8 e9 e10 e11 e12 e13 e14 e15 e16 e17 e18 f1 f2 f3 f4 f5 f7 f8 f9 f10 f11 f12 f14 f15 f16 f17 f18 g1 g2 g3 g4 g5 g6 g13 g14 g15 g16 g17 g18 h1 h2 h3 h4 h5 h6 h13 h14 h15 h16 h17 h18 j1 j2 j3 j4 j5 j6 j13 j14 j15 j16 j17 j18 k1 k2 k3 k4 k5 k6 k13 k14 k15 k16 k17 k18 l1 l2 l3 l4 l5 l6 l13 l14 l15 l16 l17 l18 m1 m2 m3 m4 m5 m6 m13 m14 m15 m16 m17 m18 n1 n2 n3 n4 n5 n7 n8 n9 n10 n11 n12 n14 n15 n16 n17 n18 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p16 p17 p18 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 v16 v17 u1 u2 u3 u4 u5 u6 u7 u8 u9 u10 u11 u12 u13 u14 u15 u16 u17 u18
TMP1962F10AXBG tmp1962f-7 table 2.1 pin cross reference by pin number (2/2) pin no. pin name pin no. pin name pin no. pin name pin no. pin name pin no. pin name d8 dvcc2 f18 p44/scout k14 p12/d10/ad10 n18 dvss t8 pd4/txd4 d9 dvss g1 reset k15 p13/d11/ad11 p1 pp0 t9 pc0/txd0 d10 pl5/tb0in1 g2 test5 k16 p14/d12/ad12 p2 pb2/tb2in0/int5 t10 pc3/txd1 d11 pm3 g3 fvcc2 k17 dvcc33 p3 pb3/tb2in1/int6 t11 ph4/tcout4 d12 pm6 g4 fvss k18 p15/d13/ad13 p4 pb4/tb2out t12 pe2/sclk5/ 5 cts d13 pk4/key4 g5 pj0/int0 l1 fvcc3 p5 pb5/tb3in0/int7 t13 pe5/keyb d14 pk7/key7 g6 bw0 l2 po1 p6 pg5/tc5in t14 p53/a3 d15 dvcc34 g13 trst l3 po2 p7 pg7/tc7in t15 p56/a6 d16 tdi (jtag) g14 cap1 l4 po3 p8 pd6/sclk4/ 4 cts t16 p62/a10 d17 tdo (jtag) g15 p41/ 1 cs l5 po4 p9 pc2/sclk0/ 0 cts t17 p65/a13 d18 xt1 g16 p37/ale l6 po7 p10 pc5/sclk1/ 1 cts t18 p20/a16/a0 e1 dclk (dsu) g17 p35/ busak l13 test3 p11 ph6/tcout6 u1 pa0/ta0in e2 pcst1 (dsu) g18 fvcc2 l14 p06/d6/ad6 p12 nc u2 pa3/ta3out e3 dbge h1 nmi l15 fvcc2 p13 p50/a0 u3 pa6/ta9out e4 pj3/intlv h2 dvcc31 l16 p07/d7/ad7 p14 p51/a1 u4 pf1/si/scl e5 pj4/endian h3 pn7 l17 p10/d8/ad8 p15 p54/a4 u5 pf5/ 3 dreq e6 p97/ain23 h4 bw1 l18 p11/d9/ad9 p16 p23/a19/a3 u6 pg2/tc2in e7 p87/ain15 h5 plloff m1 po0 p17 p24/a20/a4 u7 pd2/rxd3 e8 p76/ain6 h6 test1 m2 pp5 p18 p25/a21/a5 u8 dvcc32 e9 p77/ain7 h13 test2 m3 pp6 r1 pb0/tb0out u9 pc7/rxd2 e10 pl6/tb1in0 h14 p31/ wr m4 pp7 r2 pb1/tb1out u10 ph1/tcout1 e11 pl7/tb1in1 h15 p32/ hwr m5 pb7/tb3out r3 pf3/ 2 dreq u11 ph3/tcout3 e12 pm7 h16 p33/wait/rdy m6 dvcc32 r4 pf4/ 2 dack u12 pe1/rxd5 e13 pk5/key5 h17 p30/ rd m13 test4 r5 pf7/tbtin u13 pe4/keya e14 nc h18 p40/ 0 cs m14 p02/d2/ad2 r6 pg4/tc4in u14 dvcc32 e15 tms (jtag) j1 pn2/sclk6/ 6 cts m15 fvss r7 pg6/tc6in u15 p57/a7 e16 cvcch j2 pn3 m16 p03/d3/ad3 r8 pd5/rxd4 u16 p63/a11 e17 nc j3 pn4 m17 p04/d4/ad4 r9 pc1/rxd0 u17 p66/a14 e18 dvcc2 j4 pn5 m18 p05/d5/ad5 r10 pc4/rxd1 u18 dvcc33 f1 dvss j5 pn6 n1 pp1 r11 p h5/tcout5 v2 pa2/ta2in f2 dreset j6 dvcc2 n2 pp2 r12 ph7/tcout7 v3 pa5/ta7out f3 sysrdy j13 fvss n3 pp3 r13 pe6/keyc v4 pf0/so/sda f4 pj1/busmd j14 p16/d14/ad14 n4 pp4 r14 p52/a2 v5 pg0/tc0in f5 pj2/ boot j15 dvss n5 pb6/tb3in1/int8 r15 p55/a5 v6 pg1/tc1in f7 avss j16 p17/d15/ad15 n7 dvss r16 p61/a9 v7 pd1/txd3 f8 avss j17 p36/ w / r n8 pd7/key8 r17 p21/a17/a1 v8 pd0/sclk2/ 2 cts f9 avcc32 j18 p34/ busrq n9 dvcc2 r18 p22/a18/a2 v9 pc6/txd2 f10 dvcc34 k1 pn0/txd6 n10 dvss t1 pa1/ta1out v10 ph0/tcout0 f11 pi0/ adtrg k2 pn1/rxd6 n11 rstpup t2 pa4/ta5out v11 ph2/tcout2 f12 dvss k3 po5 n12 dvss t3 pa7/tabout v12 pe0/txd5 f14 cap2 k4 po6 n14 p26/a22/a6 t4 pf2/sck v13 pe3/key9 f15 p42/ 2 cs k5 fvss n15 p27/a23/a7 t5 pf6/ 3 dack v14 pe7/keyd f16 p43/ 3 cs k6 dvss n16 p00/d0/ad0 t6 pg3/tc3in v15 p60/a8 f17 dvcc33 k13 test0 n17 p01/d1/ad1 t7 pd3/sclk3/ 3 cts v16 p64/a12 v17 p67/a15
TMP1962F10AXBG tmp1962f-8 2.2 pin usage information table 2.2 lists input and output pins of the TMP1962F10AXBG. table 2.2 pin names and function (1/6) pin name # of pins type function p00-p07 d0-d7 ad0-d7 8 input/output input/output input/output port 0: individually programmable input or output data (lower): bits 0-7 of the data bus (separate bus mode) address /data (lower): bits 0-7 of t he address/data bus (multiplex bus mode) p10-p17 d8-d15 ad8-ad15 a8-a15 8 input/output input/output input/output output port 1: individually programmable input or output data (upper): bits 8-15 of the data bus (separate bus mode) address /data (upper): bits 8-15 of t he address/data bus (multiplex bus mode) address: bits 8-15 of the address bus (multiplex bus mode) p20-p27 a16-a23 a0-a7 a16-a23 8 input/output output output output port 2: individually programmable input or output address: bit 15-23 of the address bus (separate bus mode) address: bit 0-7 of the address bus (multiplex bus mode) address: bit 16-23 of the address bus (multiplex bus mode) p30 rd 1 output output port 30: output-only read strobe: asserted during a read operation from an external memory device p31 wr 1 output output port 31: output-only write strobe: asserted during a write operation on d0-d7 p32 hwr 1 input/output output port 32: programmable as input or output (with internal pull-up register) higher write strobe: asserted during a write operation on d8-d15 p33 wait rdy 1 input/output input input port 33: programmable as input or output (with internal pull-up resister) wait: causes the cpu to sus pend external bus activity ready: informs the cpu of bus ready condition p34 busrq 1 input/output input port 34: programmable as input or output (with internal pull-up resister) bus request: asserted by an external bus master to request bus mastership p35 busak 1 input/output output port 35: programmable as input or output (with internal pull-up resister) bus acknowledge: indicates that the cp u has relinquished the bus in response to busrq . p36 w / r 1 input/output output port 36: programmable as input or output (with internal pull-up resister) read/write: indicates the direction of data transfer on the bus: 1 = read or dummy cycle, 0 = write cycle p37 ale 1 input/output output port 37: programmable as input or output address latch enable (this signal is dr iven out only when external memory is accessed.) p40 0 cs 1 input/output output port 40: programmable as input or output (with internal pull-up resister) chip select 0: asserted low to enable external devices at programmed addresses p41 1 cs 1 input/output output port 41: programmable as input or output (with internal pull-up resister) chip select 1: asserted low to enable external devices at programmed addresses p42 2 cs 1 input/output output port 42: programmable as input or output (with internal pull-up resister) chip select 2: asserted low to enable external devices at programmed addresses p43 3 cs 1 input/output output port 43: programmable as input or output (with internal pull-up resister) chip select 3: asserted low to enable external devices at programmed addresses p44 scout 1 input/output output port 44: programmable as input or output system clock output: drives out a clock signal at the frequency equal to or one half of cpu clock (high-speed or low-speed) p50-p57 a0-a7 8 input/output output port 5: individually programmable as input or output address: address bus 0-7 (separate bus mode) p60-p67 a8-a15 8 input/output output port 6: individually programmable as input or output address: address bus 8-15 (separate bus mode) p70-p77 an0-an7 8 input input port 7: input-only analog input: input to the on-chip a/d converter p80-p87 an8-an15 8 input input port 8: input-only analog input: input to the on-chip a/d converter
TMP1962F10AXBG tmp1962f-9 table 2.2 pin names and function (2/6) pin name # of pins type function p90-p97 an16-an23 8 input input port 9: input-only analog input: input to the on-chip a/d converter pi0 adtrg 1 input/output input port i0: programmable as input or output ad trigger: starts an a/d conversion schmitt trigger input pi1 int1 1 input/output input port i1: programmable as input or output interrupt request 1: programmable to be high-level, low-level, rising-edge or falling-edge sensitive schmitt trigger input pi2 int2 1 input/output input port i2: programmable as input or output interrupt request 2: programmable to be high-level, low-level, rising-edge or falling-edge sensitive schmitt trigger input pi3 int3 1 input/output input port i3: programmable as input or output interrupt request 3: programmable to be high-level, low-level, rising-edge or falling-edge sensitive schmitt trigger input pi4 int4 1 input/output input port i4: programmable as input or output interrupt request 4: programmable to be high-level, low-level, rising-edge or falling-edge sensitive schmitt trigger input pi5 int9 1 input/output input port i5: programmable as input or output interrupt request 9: programmable to be high-level, low-level, rising-edge or falling-edge sensitive schmitt trigger input pi6 inta 1 input/output input port i6: programmable as input or output interrupt request a: programmable to be high-level, low-level, rising-edge or falling-edge sensitive schmitt trigger input pi7 1 input/output port i7: programmable as input or output pa0 ta0in 1 input/output input port a0: programmable as input or output 8-bit timer 0 input: input to 8-bit timer 0 pa1 ta1out 1 input/output output port a1: programmable as input or output 8-bit timer 01 output: output from either 8-bit timer 0 or timer 1 pa2 ta2in 1 input/output input port a2: programmable as input or output 8-bit timer 2 input: input to 8-bit timer 2 pa3 ta3out 1 input/output output port a3: programmable as input or output 8-bit timer 23 output: output from either 8-bit timer 2 or timer 3 pa4 ta5out 1 input/output output port a4: programmable as input or output 8-bit timer 45 output: output from either 8-bit timer 4 or timer 5 pa5 ta7out 1 input/output output port a5: programmable as input or output 8-bit timer 67 output: output from either 8-bit timer 6 or timer 7 pa6 ta9out 1 input/output input port a6: programmable as input or output 8-bit timer 89 output: output from either 8-bit timer 8 or timer 9 pa7 tabout 1 input/output output port a7: programmable as input or output 8-bit timer ab output: output from either 8-bit timer a or timer b pb0 tb0out 1 input/output output port b0: programmable as input or output 16-bit timer 0 output: output from 16-bit timer 0 pb1 tb1out 1 input/output output port b1: programmable as input or output 16-bit timer 1 output: output from 16-bit timer 1 pb2 tb2in0 int5 1 input/output input input port b2: programmable as input or output 16-bit timer 2 input 0: count/captur e trigger input to 16-bit timer 2 interrupt request 5: programmable to be high-level, low-level, rising-edge or falling-edge sensitive
TMP1962F10AXBG tmp1962f-10 table 2.2 pin names and function (3/6) pin name # of pins type function pb3 tb2in1 int6 1 input/output input input port b3: programmable as input or output 16-bit timer 2 input 1: capture trigger input to 16-bit timer 2 interrupt request 6: programmable to be high-level, low-level, rising-edge or falling-edge sensitive pb4 tb2out 1 input/output output port b4: programmable as input or output 16-bit timer 2 output: output from 16-bit timer 2 pb5 tb3in0 int7 1 input/output input input port b5: programmable as input or output 16-bit timer 3 input 0: count/captur e trigger input to 16-bit timer 3 interrupt request 7: programmable to be high-level, low-level, rising-edge or falling-edge sensitive pb6 tb3in1 int8 1 input/output input input port b6: programmable as input or output 16-bit timer 3 input 1: capture trigger input to 16-bit timer 3 interrupt request 8: programmable to be high-level, low-level, rising-edge or falling-edge sensitive pb7 tb3out 1 input/output output port b7: programmable as input or output 16-bit timer 3 output: output from 16-bit timer 3 pc0 txd0 1 input/output output port c0: programmable as input or output serial transmit data 0: programmabl e as a push-pull or open-drain output pc1 rxd0 1 input/output input port c1: programmable as input or output serial receive data 0 pc2 sclk0 0 cts 1 input/output input input port c2: programmable as input or output serial clock input/output 0 serial clear-to-send 0 programmable as a push-pull or open-drain output pc3 txd1 1 input/output output port c3: programmable as input or output serial transmit data 1: programmabl e as a push-pull or open-drain output pc4 rxd1 1 input/output input port c4: programmable as input or output serial receive data 1 pc5 sclk1 1 cts 1 input/output input input port c5: programmable as input or output serial clock input/output 1 serial clear-to-send 1 programmable as a push-pull or open-drain output pc6 txd2 1 input/output output port c6: programmable as input or output serial transmit data 2: programmabl e as a push-pull or open-drain output pc7 rxd2 1 input/output input port c7: programmable as input or output serial receive data 2 pd0 sclk2 2 cts 1 input/output input input port d0: programmable as input or output serial clock input/output 2 serial clear-to-send 2 programmable as a push-pull or open-drain output pd1 txd3 1 input/output output port d1: programmable as input or output serial transmit data 3: programmabl e as a push-pull or open-drain output pd2 rxd3 1 input/output input port d2: programmable as input or output serial receive data 3 pd3 sclk3 3 cts 1 input/output input input port d3: programmable as input or output serial clock input/output 3 serial clear-to-send 3 programmable as a push-pull or open-drain output pd4 txd4 1 input/output output port d4: programmable as input or output serial transmit data 4: programmabl e as a push-pull or open-drain output pd5 rxd4 1 input/output input port d5: programmable as input or output serial receive data 4 pd6 sclk4 4 cts 1 input/output input input port d6: programmable as input or output serial clock input/output 4 serial clear-to-send 4 programmable as a push-pull or open-drain output pd7 key8 1 input/output input port d7: programmable as input or output key on wake up input 8: (dynamic pull-up se lectable) (with internal pull-up register) schmitt trigger input
TMP1962F10AXBG tmp1962f-11 table 2.2 pin names and function (4/6) pin name # of pins type function pe0 txd5 1 input/output output port e0: programmable as input or output serial transmit data 5: programmabl e as a push-pull or open-drain output pe1 rxd5 1 input/output input port e1: programmable as input or output serial receive data 5 pe2 sclk5 5 cts 1 input/output input input port e2: programmable as input or output serial clock input/output 5 serial clear-to-send 5 programmable as a push-pull or open-drain output pe3 key9 1 input/output input port e3: programmable as input or output key on wake up input 9: (dynamic pull-up se lectable) (with internal pull-up register) schmitt trigger input pe4 keya 1 input/output input port e4: programmable as input or output key on wake up input a: (dynamic pull-up se lectable) (with internal pull-up register) schmitt trigger input pe5 keyb 1 input/output input port e5: programmable as input or output key on wake up input b: (dynamic pull-up se lectable) (with internal pull-up register) schmitt trigger input pe6 keyc 1 input/output input port e6: programmable as input or output key on wake up input c: (dynamic pull-up se lectable) (with internal pull-up register) schmitt trigger input pe7 keyd 1 input/output input port c7: programmable as input or output key on wake up input d: (dynamic pull-up se lectable) (with internal pull-up register) schmitt trigger input pf0 so sda 1 input/output output input/output port f0: programmable as input or output data transmit pin when the serial bus interface is in sio mode data transmit/receive pin when the seri al bus interface is in i2c mode; programmable as a push-pull or open-drain output schmitt trigger input pf1 si scl 1 input/output input input/output port f1: programmable as input or output data receive pin when the serial bus interface is in sio mode clock input/output pin when the serial bus interface is in i2c mode; programmable as a push-pull or open-drain output schmitt trigger input pf2 sck 1 input/output input/output port f2: programmable as input or output clock input/output pin when the serial bus interface is in sio mode pf3 2 dreq 1 input/output input port f3: programmable as input or output dma request 2: dma transfer request from an external i/o device to dmac2 pf4 2 dack 1 input/output output port f4: programmable as input or output dma acknowledge 2: acknowledge signal for dma transfer requested by dreq2 pf5 3 dreq 1 input/output input port f5: programmable as input or output dma request 3: dma transfer request from an external i/o device to dmac3 pf6 3 dack 1 input/output output port f6: programmable as input or output dma acknowledge 3: acknowledge signal for dma transfer requested by dreq3 pf7 tbtin 1 input/output input port f7: programmable as input or output 32-bit time-base timer input: count input to 32-bit time-base timer pg0-pg7 tc0in-tc7in 8 input/output input port g: individually programmable as input or output 32-bit timer capture trigger input ph0-ph7 tcout0-tco ut7 8 input/output output port h: individually programmable as input or output 32-bit timer compare match output pj0 int0 1 input/output input port j0: programmable as input or output interrupt request 0: programmable to be high-level, low-level, rising-edge or falling-edge sensitive schmitt trigger input
TMP1962F10AXBG tmp1962f-12 table 2.2 pin names and function (5/6) pin name # of pins type function pj1 busmd 1 input/output input port j1: programmable as input or output external bus mode: if this pin is sampled high (dvcc21) at the rising edge of reset, the TMP1962F10AXBG enters multiplex bus mode. if this pin is sampled low at the rising edge of reset, the TMP1962F10AXBG enters separate bus mode. during a reset sequence, this pin should be pulled up to a logic 1or pulled down to a logic 0 depending on the bus mode to be used. pj2 boot 1 input/output input port j2: programmable as input or output single boot mode: if this pin is samp led low at the rising edge of reset, the TMP1962F10AXBG enters single boot mode for re-programming of the on-chip flash. if this pin is sampled high (dvcc21) at the rising edge of reset, the TMP1962F10AXBG enters normal mode. duri ng a reset sequence, this pin should be pulled up to a logic 1 commonly. pj3 intlv 1 input/output input port j3: programmable as input or output interleave mode: the TMP1962F10AXBG enter s interleave mode when this pin is sampled high (dvcc21) at the rising edge of reset. during a reset sequence, this pin should be pulled up to a logic 1. pj4 endian 1 input/output input port j4: programmable as input or output this pin is used to set the mode. if this pin is sampled high (dvcc21) at the rising edge of reset, the TMP1962F10AXBG enters big-endian mode. if this pin is sampled low at the rising edge of reset, the TMP1962F10AXBG enters little-endian mode. during a reset sequence, this pin shoul d be pulled up to a logic 1or pulled down to a logic 0 depending the endian to be used. pk0-pk7 key0-key7 8 input/output input port k: programmable as input or output key on wake up input 0-7 (dynamic pull-up se lectable) (with internal pull-up register) schmitt trigger input pl0 ta4in 1 input/output input port l0: programmable as input or output 8-bit timer 4 input: input to 8-bit timer 4 pl1 ta6in 1 input/output input port l1: programmable as input or output 8-bit timer 6 input: input to 8-bit timer 6 pl2 ta8in 1 input/output input port l2: programmable as input or output 8-bit timer 8 input: input to 8-bit timer 8 pl3 taain 1 input/output input port l3: programmable as input or output 8-bit timer a input: input to 8-bit timer a pl4 tb0in0 1 input/output input port l4: programmable as input or output 16-bit timer 0 input 0: count/captur e trigger input to 16-bit timer 0 pl5 tb0in1 1 input/output input port l5: programmable as input or output 16-bit timer 0 input 1: capture trigger input to 16-bit timer 0 pl6 tb1in0 1 input/output input port l6: programmable as input or output 16-bit timer 1 input 0: count/captur e trigger input to 16-bit timer 1 pl7 tb1in1 1 input/output input port l7: programmable as input or output 16-bit timer 1 input 1: capture trigger input to 16-bit timer 1 pm0-pm7 8 input/output port m: individually programmable input or output pn0 txd6 1 input/output output port n0: programmable as input or output serial transmit data 6: programmabl e as a push-pull or open-drain output pn1 rxd6 1 input/output input port n1: programmable as input or output serial receive data 6 pn2 sclk6 6 cts 1 input/output input input port n2: programmable as input or output serial clock input/output 6 serial clear-to-send 6 programmable as a push-pull or open-drain output pn3-pn7 5 input/output port n3-n7: individually programmable input or output po0-po7 8 input/output port o: individually programmable input or output pp0-pp7 8 input/output port p: individually programmable input or output
TMP1962F10AXBG tmp1962f-13 table 2.2 pin names and function (6/6) pin name # of pins type function nmi 1 input nonmaskable interrupt request: causes an nmi interrupt on the falling edge plloff 1 input this pin should be tied to high (dvcc21) when the frequency multiplied clock from the pll is used; otherwise, it should be tied to low. schmitt trigger input rstpup 1 input during a reset sequence, port 3 and port 4 are pull-up enabled if this pin is sampled high (dvcc32), and disabled if this pin is sampled low. schmitt trigger input reset 1 input reset (with internal pull-up register): initializes the whole TMP1962F10AXBG schmitt trigger input x1/x2 2 input/output connection pins for a high-speed crystal xt1/xt2 2 input/output this pin should be left open. dreset 1 input debug reset: signal for dsu- ice (schmitt tri gger input, with internal pull-up register) dclk 1 output debug clock: signal for dsu-ice dbge 1 input debug enable: signal for dsu-ice (schmitt tri gger input, with internal pull-up register) pcst3-0 4 output pc trace status: signal for dsu-ice sdi/ dint 1 input serial data input/debug interrupt: signal for dsu-ice (schmitt trigger input, with internal pull-up register) sdao/tpc 1 output serial data and address output/target pc: signal for dsu-ice tck 1 input test clock input: signal for jtag test (s chmitt trigger input, with internal pull-up register) tms 1 input test mode select input: signal for jtag te st (schmitt trigger input, with internal pull-up register) tdi 1 input test data input: signal for jtag test (s chmitt trigger input, with internal pull-up register) tdo 1 output test data output: signal for jtag test trst 1 input test reset input: signal for jtag test (s chmitt trigger input, with internal pull-up register) bw0-1 2 input both bw0 and bw1 should be tied to hi gh (dvcc21). (schmitt trigger input) vrefh 1 input input pin for high reference voltage for the a/d converter this pin should be connected to the avcc pi n when the a/d converter is not used. vrefl 1 input input pin for low reference voltage for the a/d converter this pin should be connected to the avcc pi n when the a/d converter is not used. avcc31-32 2 ? power supply pins for the a/d converter. these pins should al ways be connected to power supply even when the a/d converter is not used. avss 3 ? ground pins for the a/d converter. these pi ns should always be connected to ground even when the a/d converter is not used. test0 1 ? test pin: this pin should be left open or tied to ground. test1 1 input test pin: this pin should be tied to ground. test2 1 ? test pin: this pin should be left open or tied to ground. test3 1 ? test pin: this pin should be left open or tied to ground. test4 1 ? test pin: this pin should be left open or tied to ground. test5 1 input test pin: this pin should be tied to ground. sysrdy 1 output signal to grant access to a flash memory cvcc2 1 ? power supply pins for an oscillator: 2.5 v cvss 1 ? ground pin for an oscillator (0 v) cvcch 1 ? this pin should be left open. cap1 1 ? this pin should be left open. cap2 1 ? this pin should be left open. fvcc2 3 ? power supply pins for a flash memory: 2.5 v fvcc3 1 ? power supply pin for a flash memory: 3 v fvss 4 ? ground pins for a flash memory (0 v) dvcc21-22 5 ? power supply pins: 2.5 v dvcc31-34 9 ? power supply pins: 3 v dvss 9 ? ground pins (0v)
TMP1962F10AXBG tmp1962f-14 note 1: pj1, pj2, pj3 and pj4 should be held at the prescribed logic states for one system clock cycle before and after the rising edge of reset, with the reset signal being stable in either logic state. note 2: debugging with a dsu-probe is enabled on the tmp 1962f10axbg. connection to the dsu-probe is available on the tmp1962c10bxbg, but a dsu-probe can not read the contents of on-chip rom or write to registers other than the processor core, on-chip memory and external device. table 2.3 shows correspondence between pins and power supply pins. table 2.3 pins and corresponding power supply pins power supply power supply pin mask type flash type pin mask type flash type p0 dvcc33 dvcc33 po dvcc31 dvcc31 p1 dvcc33 dvcc33 pp dvcc31 dvcc31 p2 dvcc33 dvcc33 x1 cvcc15 cvcc2 p3 dvcc33 dvcc33 x2 cvcc15 cvcc2 p4 dvcc33 dvcc33 reset dvcc2 dvcc21 p5 dvcc33 dvcc33 nmi dvcc2 dvcc21 p6 dvcc33 dvcc33 plloff dvcc2 dvcc21 p7 avcc32 avcc32 dreset dvcc2 dvcc21 p8 avcc32 avcc32 dclk dvcc2 dvcc21 p9 avcc31 avcc31 dbge dvcc2 dvcc21 pa dvcc32 dvcc32 pcst3-0 dvcc2 dvcc21 pb dvcc32 dvcc32 sdi/ dint dvcc2 dvcc21 pc dvcc32 dvcc32 sdao/tpc dvcc2 dvcc21 pd dvcc32 dvcc32 tck dvcc34 dvcc34 pe dvcc32 dvcc32 tms dvcc34 dvcc34 pf dvcc32 dvcc32 tdi dvcc34 dvcc34 pg dvcc32 dvcc32 tdo dvcc34 dvcc34 ph dvcc32 dvcc32 trst dvcc34 dvcc34 pi dvcc34 dvcc34 bw1-0 dvcc2 dvcc21 pj dvcc2 dvcc21 rstpup dvcc32 dvcc32 pk dvcc34 dvcc34 pl dvcc34 dvcc34 pm dvcc34 dvcc34 pn dvcc31 dvcc31
TMP1962F10AXBG tmp1962f-15 table 2.4 shows the supply voltage for power supply pins. table 2.4 supply voltage for power supply pins power supply pin supply voltage applied for dvcc15 1.35 v - 1.65 v cvcc15 1.35 v - 1.65 v dvcc2 2.3 v - 3.3 v mask type dvcc21 2.2 v - 2.7 v dvcc22 2.2 v - 2.7 v cvcc2 2.2 v - 2.7 v fvcc2 2.2 v - 2.7 v fvcc3 2.9 v - 3.6 v flash type dvcc31 - 34 1.65 v - 3.3 v avcc31 - 32 2.7 v - 3.3 v mask/flash type note 1: avcc32 avcc31 ? when p7 to p9 are used as a/d converter inputs: 2.7 avcc3 * ? when p9 (powered by avcc31) is used as an a/d converter input while p7 and p8 (powered by avcc32) are used as ports: 2.7 v avcc31 3.3 v 1.65 v avcc32 avcc31 ? when p7 (powered by avcc32) is used as an a/d converter input which p8 (powered by avcc32) and p9 (powered by avcc31) are used as ports: 2.7 v avcc32 avcc31 3.3 v note2: with power supplies for cpu and internal logic (mask type: dvcc15/dvcc2/dvcc15, and flash type: dvcc21/dvcc22/cvcc2/fvcc2/fvcc3) being applied, power supplies for other i/o ports can be interrupted on the tmp1962. however, when avcc31 for analog power supply is interrupted, overlap current is generated on the tmp1962f10a with on-chip flash memory during the transition to be stable in 0 v. overlap current can be suppressed by ad conversion of the conversion result 0 v before interrupting avcc31 power supply, but suppress it on devices.
TMP1962F10AXBG tmp1962f-15 3. flash memory this chapter describes the flash memory of the TMP1962F10AXBG, a flash version of the tmp1962c10bxbg. the TMP1962F10AXBG contains a 1-mbyte flash eeprom and 40-kbyte ram whereas the tmp1962c10bxbg contains a 1-mbyte rom and a 40-kbyte ram. in other respects, the hardware configuration and the functionality of the tmp1962f10 axbg are identical to those of the tmp1962c10bxbg. for descriptions of the on-chip i/o peripherals, refer to the tmp1962c10bxbg datasheet. 3.1 features (1) organization the TMP1962F10AXBG contains 8 mbits (1024 kbytes) of flash memory, which is divided into a total of 8 blocks (128-kbyte x 8) to allow for independent protection from program and erase for each block. while the cpu can access information in the flash th rough a full 32-bit data bu s, an external flash programmer can only perform 16-bit data bus writes to the flash. (2) access types the flash memory of the TMP1962F10AXBG provides the interleaved access type. (3) program/erase time ? chip programming time: 15 seconds (typ.) including verify operations ? chip erase time: 40 seconds (typ.), including verify operations (4) programming modes several options exist to program the TMP1962F10AXBG flash memory. on-board programming modes allow for re-programming of the flash memory while the chip is soldered on a printed circuit board. programmer mode utilizes an eprom programmer to perform code updates. ? on-board programming modes 1) user boot mode supports use of a user-wr itten programming algorithm. 2) single boot mode downloads the new program code using a toshiba-defined serial interface protocol. ? programmer mode supports use of a general-purpose eprom programmer. (5) re-programming the TMP1962F10AXBG flash memory is compatible with the jedec standards, except a few unique functions. thus, it is easy to migrate from a discrete flash memory device to the on-chip flash memory of the TMP1962F10AXBG. the TMP1962F10AXBG contains hardware to perform programming and erase operations automatically. this eliminates the ne ed for the user to code complex program and erase sequences. the security feature of the TMP1962F10AXBG flash memory prevents the stored data from being read while it is being re-programmed with programming equipment. the TMP1962F10AXBG also allows the user to protect individual blocks of the flash memory against program or erase through software commands; however, 12-v vpp programming does not support data protection on a block-by-block basis. the flash memory is secured automatically by all of 8 blocks being protected. unsecuring the flash memory automatically erases the stored data prior to unprotecting the blocks. note: these program and erase times are typical values and do not include data transfer overhead. the actual chip program and erase times depend on the programming method used.
TMP1962F10AXBG tmp1962f-16 jedec standard changes and enhancements auto program auto chip erase auto block erase auto multi-block erase data polling / toggle bit added feature: security auto program changed feature: block protection is available only under software control. removed feature: erase resume/suspend mode 3.2 block diagram rom controller / interleave control mode setup pins control a ddress data flash memory column decoder / sense amp data latch address latch erase block decoder control logic (including automatic sequence control logic) command register rdy/bsy output internal address bus internal data bus internal control bus flash memory array 1024 kb row decoder mode control figure 3.1 flash memory block diagram
TMP1962F10AXBG tmp1962f-17 3.3 operating modes 3.3.1 overview the TMP1962F10AXBG offers a total of five operating modes, including the one in which the flash memory is unused. table 3.1 operating modes operating mode description single-chip mode normal mode user boot mode after a reset, the tx19 core processor executes ou t of the on-chip flash memory. set the intlv pin to high level when reset is released. single-chip mode is further divided into normal mode in which the user application executes and user boot mode which allows for re-programming of the flash memory while the TMP1962F10AXBG is installed on a printed circuit board. the user can freely define how to switch between normal mode and user boot mode. for example, the logic state on, say, port 00, can be used to determine whether to put the flash memory in normal mode or user boot mode. the user must include a routine in the application program to test the state of that port. single boot mode after a reset, the tx19 core processor ex ecutes out of the on-chip boot rom (which is a mask rom). the boot rom contains a routine to ai d users in performing on-board programming of the flash memory via a serial port of the tmp1962f10a xbg. the serial port is connected to an external host which transfers new data according to a prescribed protocol. programmer mode this mode allows re-programming of the flash memory with a general-purpose eprom programmer. use the programmer and programming adaptor recommended by toshiba. the on-chip flash memory can be re-programmed in one of the following three modes: user boot mode, single boot mode and programmer mode. of these modes, user boot mode and single boot mode are collectively referred to as on-board programming modes. the logic states on the bw0, bw1, boot and intlv pins during a reset sequence determine the mode of operation for the flash memory, as shown in table 3.2. after reset is released, pj2 ( boot ) and pa2 (intlv) can be configured as general-purpose i/o pins. after a reset, the cpu operates in compliance with the selected mode , except for programmer mode. when programmer mode is selected, reset must be held at logic 0. the input pins listed in table 3.2 must remain stable once the flash memory is put in a given mode of operation. table 3.2 modes of operation input pins # operating mode reset bw0 bw1 reset intlv (1) single-chip mode 0 1 1 1 1 1 (2) single boot mode 0 1 1 1 0 note 1 (3) programmer mode 0 0 1 note 1 note 1 note 1: don?t care. the pins must be held at 1 or 0, however.
TMP1962F10AXBG tmp1962f-18 figure 3.2 mode transitions 3.3.2 reset operation to reset the TMP1962F10AXBG, reset must be asserted for at least 12 system clock periods after the power supply voltage and the internal high-frequency oscillator have stabilized. this time is typically 2.37 s at 40.5 mhz when the on-chip pll is utilized. programmer m ode on-board programming mode reset = 0 reset = 0 (2) (3) (1) user-defined condition single-chip mode reset any condition other than (4) + reset = 0 normal mode user boot mode single boot mode parenthesized numbers indicate that the relevant pins are at the logic states shown in table 3.2.
TMP1962F10AXBG tmp1962f-19 3.3.3 memory maps the memory map for the TMP1962F10AXBG varies according to the operation mode selected for the on-chip flash memory. following are the memory maps in each operation mode. note: the addresses shown above are physical addresses. figure 3.3 TMP1962F10AXBG memory maps figure 3.4 flash memory block architecture on-chip peripherals normal mode single boot mode programmer mode 0xffff_ffff 0xc000_0000 0x4000_0000 0x2000_0000 0x000f_ffff 0x0000_0000 0xffff_ffff 0xffff_e000 0xfffd_ffff 0xfffd_6000 0xff3f_ffff 0xff20_0000 0xc000_0000 0x400f_ffff 0x4000_0000 0x1fcf_ffff 0x1fc0_0400 0x1fc0_0000 0x2000_0000 0x0000_0000 0xff00_0000 0xbf00_0000 0x1fc0_1fff 0xffff_ffff 0xffff_e000 0xfffd_dfff 0xfffd_6000 0xff3f_ffff 0xff20_0000 0xc000_0000 0x400f_ffff 0x4000_0000 0x2000_0000 0x1fc0_0000 0x0000_0000 0xff00_0000 0xbf00_0000 (reserved) on-chip ram (40 kb) (reserved) used for debugging (reserved) (reserved) (reserved) on-chip rom shadow inaccessible (512 mb) user program area maskable interrupt area exception vector area on-chip peripherals (reserved) on-chip ram (40 kb) (reserved) used for debugging (reserved) (reserved) (reserved) on-chip flash inaccessible (512 mb) boot rom (8 kb) inaccessible inaccessible inaccessible (512 mb) inaccessible on-chip flash 128 kb 1024 kb 128 kb 128 kb 128 kb 128 kb 128 kb 128 kb 128 kb block-0 block-1 block-2 block-3 block-4 block-5 block-6 block-7
TMP1962F10AXBG tmp1962f-20 table 3.3 block addresses user boot mode boot mode programmer mode block-0 0x1fc0_0000 - 0x1fc1_ffff (or 0x4000_0000 - 0x4001_ffff) 0x1fc0_0000 - 0x1fc1_ffff 0x0000_0000 - 0x0001_ffff block-1 0x1fc2_0000 - 0x1fc3_ffff (or 0x4002_0000 - 0x4003_ffff) 0x1fc2_0000 - 0x1fc3_ffff 0x0000_8000 - 0x0003_ffff block-2 0x1fc4_0000 - 0x1fc5_ffff (or 0x40040000 - 0x4005_ffff) 0x1fc4_0000 - 0x1fc5_ffff 0x0001_0000 - 0x0005_ffff block-3 0x1fc6_0000 - 0x1fc7_ffff (or 0x4006_0000 - 0x4007_ffff) 0x1fc6_0000 - 0x1fc7_ffff 0x0001_8000 - 0x0007_ffff block-4 0x1fc8_0000 - 0x1fc9_ffff (or 0x4008_0000 - 0x4009_ffff) 0x1fc8_0000 - 0x1fc9_ffff 0x0002_0000 - 0x0009_ffff block-5 0x1fca_0000 - 0x1fcb_ffff (or 0x400a_0000 - 0x400b_ffff) 0x1fca_0000 - 0x1fcb_ffff 0x0002_8000 - 0x000a_ffff block-6 0x1fcc_0000 - 0x1fcd_ffff (or 0x400c_0000 - 0x400d_ffff) 0x1fcc_0000 - 0x1fcd_ffff 0x0003_0000 - 0x000b_ffff block-7 0x1fce_0000 - 0x1fcf_ffff (or 0x400e_0000 - 0x400f_ffff) 0x1fce_0000 - 0x1fcf_ffff 0x0003_8000 - 0x000c_ffff 3.3.4 interleave mode if j3 (pj3) is sampled high at the rising edge of reset , the flash memory enters interleave mode. the flash memory must be configured into interleave mode. 3.3.5 block protection the TMP1962F10AXBG flash memory is organized into a total of 8 blocks (128 kbyte 8). to protect stored data from any program and erase operations, each block has a protect bit, which can be set by executing the block protect command se quence. blocks in protection mode are protected from even the chip erase and multi-block erase commands; these commands erase only unprotected blocks. since protection status is stored in flash memory cells, it is retained if the chip is powered off. when all blocks are protected, the data stored in these blocks are protected from being read in programmer mode, which provides a security feature.
TMP1962F10AXBG tmp1962f-21 3.3.6 dsu-probe interface the dsu-probe interface is used for software debugging using an external dsu-probe unit. this serves as an interface to the dsu-probe, and can not be used as general-purpose port. consult the dsu-probe operation manual for a description of debugging using thedsu-probe. when the TMP1962F10AXBG is in dsu mode, the on-chip flash memory provides a security feature. (1) flash security feature the TMP1962F10AXBG supports on-board debugging while it is installed on a printed circuit board. the TMP1962F10AXBG provides a security feature to pr event intrusive access to the flash memory. when the flash memory is in the secure state, a dsu-probe is denied access to the entirety of the flash memory. (2) securing the flash (disabling debugging with a dsu-probe) once program debug is completed, write the protect command to all of 8 blocks. this turns on the flash security feature. while the flash memory is in the secure state, a ds u-probe can not read its contents. when the chip is powered off and powered on again, the flash memory is secured, which disables debugging using a dsu-probe until the flash memory is unsecured. (3) unsecuring the flash (enabling debugging with a dsu-probe) the flash memory may only be unsecured by clearing the seqon bit in the seqmod register and then writing a special code (0x0000_00c5) to th e security control (seq cnt) register. this prevents runaway software from inadvertently turni ng off the security featur e. unsecuring the flash memory enables the dsu interface. the flash memo ry can be secured agai n by setting the seqon bit in the seqmod and writing 0x0000_00c5 to the seqcnt while the chip is powered. 7 6 5 4 3 2 1 0 seqmod name ? ? ? ? ? ? ? seqon (0xffff_e510) read/write ? ? ? ? ? ? ? r/w reset value ? ? ? ? ? ? ? 1 function 1: security on 0: security off note: this register must be read as a 32-bit quantity. bits 1 to 31 are read as 0s.
TMP1962F10AXBG tmp1962f-22 7 6 5 4 3 2 1 0 seqcnt name (0xffff_e514) read/write w reset value function must be written as 0x0000_00c5. 15 14 13 12 11 10 9 8 name read/write w reset value function must be written as 0x0000_00c5. 23 22 21 20 19 18 17 16 name read/write w reset value function must be written as 0x0000_00c5. 31 30 29 28 27 26 25 24 name read/write w reset value function must be written as 0x0000_00c5. (4) application example the following flowchart exemplifies how to use the security feature with a dsu-ice. figure 3.5 using the security feature security remains on. dsu-ice can be used until the chip is powered off. TMP1962F10AXBG security on at power-up protect/unprotect judgment routine (user-created) turn off security feature? program seqmod and seqcnt to turn off security feature dsu-ice can not be used. yes no external port data, etc. note 1: this register is read as a 32-bit quantity. note 2: the security feature of the TMP1962F10AXBG flash memory is not intended to guarantee rigid security protection. in cases where security protection is of utmost importance, use the tmp1962c10bxbg that contains mask rom.
TMP1962F10AXBG tmp1962f-23 3.4 on-board programming mode on-board programming modes allo w for re-programming of the flash memory while the TMP1962F10AXBG is soldered on a printed circuit board. in single boot mode, new data comes from a serial port under control of a toshiba-provided routine in the boot rom. user boot mode allows you to create an algorithm of your own for flash memory erase and program operations. the TMP1962F10AXBG flash memory provides a securi ty feature to prevent in trusive access to the flash memory while in programmer mode. this security feature can be enabled upon completion of on-board programming to reduce the potential risk of software leaks to third parties. 3.4.1 user boot mode (single-chip mode) user boot mode allows you to create a programming algorithm of your own. this mode supports situations where the flash memory is to be re-progra mmed via a bus other than serial i/o. user boot mode is one of the two submodes in single-chip mode; the other submode is normal mode in which the cpu executes the user application. to re-program the flash memory, the mode of operation must be switched from normal mode to user boot mode. the user application code must include a mode judgment routine as part of the reset procedure. the user must define the conditions for mode switching, based on the logic states on i/o ports of the TMP1962F10AXBG. additionally, the user must in corporate a programming algorithm into the user application code that is to be executed after user boot mode is entered. it is not possible to read from the flash memory wh ile it is being erased or programmed; th erefore, the programming algorithm must be placed and executed outside of the flash memory. once re-programming is complete, it is recommended to protect relevant flash blocks from accidental corruption. all interrupts including the nonmaskable (nmi) interrupt must be globally disabled while the flash memory is being erased or programmed. the pages that follow describe the general procedur es for two cases where the programming routine is: a) stored within the TMP1962F10AXBG flash memory, and b) loaded from an ex ternal controller. for a detailed description of the erase and pr ogram sequence, refer to section 3.6, on-board programming and erasure.
TMP1962F10AXBG tmp1962f-24 (1-a) method 1: storing a programming routine in the flash memory (1) determine the conditions (e.g., pin states) require d for the flash memory to enter user boot mode and the i/o bus to be used to transfer new program code. create hardware and software accordingly. before installing the TMP1962F10AXBG on a printed circuit board, write the following program routines into an arbitrary flash block using programming equipment. ? mode judgment routine: code to determine whether or not to switch to user boot mode ? programming routine: code to download new program code from a host controller and re-program the flash memory ? copy routine: code to copy the flash programming routine from the TMP1962F10AXBG flash memory to either the TMP1962F10AXBG on-chip ram or external memory device. (2) after reset is released, the reset procedure determines whether to put the TMP1962F10AXBG flash memory in user boot mode. if mode switching conditions are met, the flash memory enters user boot mode. (all interrupts including nmi must be globally disabled while in user boot mode.) TMP1962F10AXBG flash memory ram [reset procedure] ( a ) mode jud g ment routine old application program code host controlle r new application program code i/o (b) programming routine (c) copy routine TMP1962F10AXBG flash memory ram [reset procedure] old application program code host controlle r new application program code i/o (a) mode judgment routine (b) programming routine (c) copy routine 0 1 reset conditions for entering user boot mode (defined by the user) user boot mode
TMP1962F10AXBG tmp1962f-25 (3) once user boot mode is entered, execute the copy routine to copy the flash programming routine to either the TMP1962F10AXBG on-ch ip ram or an external memory device. (in the following figure, the on-chip ram is used.) (4) jump program execution to the flash programming routine in the on-chip ram to erase a flash block containing the old application program code. TMP1962F10AXBG flash memory ram [reset procedure] (a) mode judgment routine old application program code host controlle r new application program code i/o (b) programming routine (c) copy routine (b) programming routine TMP1962F10AXBG flash memory ram [reset procedure] (a) mode judgment routine host controlle r new application program code i/o (b) programming routine (c) copy routine (b) programming routine erased
TMP1962F10AXBG tmp1962f-26 (5) continue executing the flash programming routine to download new program code from the host controller and program it into the erased flash bl ock. once programming is complete, turn on the protection of that flash block. (6) drive reset low to reset the TMP1962F10AXBG. upon reset, the on-chip flash memory is put in normal mode. after reset is released, the cpu will start executing the new application program code. TMP1962F10AXBG flash memory ram [reset procedure] (a) mode judgment routine new application program code host controlle r new application program code i/o (b) programming routine (c) copy routine (b) programming routine TMP1962F10AXBG flash memory ram [reset procedure] (a) mode judgment routine new application program code e host controlle r (i/o) (b) programming routine (c) copy routine 0 1 reset set to normal mode
TMP1962F10AXBG tmp1962f-27 (1-b) method 2: transferring a programming routine from an external host (1) determine the conditions (e.g., pin states) require d for the flash memory to enter user boot mode and the i/o bus to be used to transfer new program code. create hardware and software accordingly. before installing the TMP1962F10AXBG on a printed circuit board, write the following program routines into an arbitrary flash block using programming equipment. ? mode judgment routine: code to determine whether or not to switch to user boot mode ? transfer routine: code to download new program code from a host controller also, prepare a programming routine on the host controller: ? programming routine: code to download new program code from an external host controller and re-program the flash memory (2) after reset is released, the reset procedure determ ines whether to put the TMP1962F10AXBG flash memory in user boot mode. if mode switching conditions are met, the flash memory enters user boot mode. (all interrupts including nmi must be globally disabled while in user boot mode.) TMP1962F10AXBG flash memory ram [reset procedure] (a) mode judgment routine old application program code host controlle r new application program code i/o (b) transfer routine (c) programming routine TMP1962F10AXBG host controlle r i/o 0 1 reset conditions for entering user boot mode (defined by the user) flash memory ram [reset procedure] ( a ) mode jud g ment routine old application program code ( b ) transfer routine new application program code (c) programming routine
TMP1962F10AXBG tmp1962f-28 (3) once user boot mode is entered, execute the transfer routine to download the flash programming routine from the host controller to either the TMP1962F10AXBG on-chip ram or an external memory device. (in the following figure, the on-chip ram is used.) (4) jump program execution to the flash programming routine in the on-chip ram to erase a flash block containing the old application program code. TMP1962F10AXBG flash memory ram [reset procedure] (a) mode judgment routine old application program code host controlle r new application program code i/o ( b ) transfer routine (c) programming routine ( c ) pro g rammin g routine TMP1962F10AXBG flash memory ram [reset procedure] (a) mode judgment routine host controlle r new application program code i/o (b) transfer routine (c) programming routine ( c ) pro g rammin g routine erased
TMP1962F10AXBG tmp1962f-29 (5) continue executing the flash programming routine to download new program code from the host controller and program it into the erased flash bl ock. once programming is complete, turn on the protection of that flash block. (6) drive reset low to reset the TMP1962F10AXBG. upon reset, the on-chip flash memory is put in normal mode. after reset is released, the cpu will start executing the new application program code. TMP1962F10AXBG flash memory ram [reset procedure] (a) mode judgment routine new application program code host controlle r new application program code i/o (b) transfer routine (c) programming routine (c) programming routine TMP1962F10AXBG host controlle r i/o 0 1 reset set to normal mode flash memory ram [reset procedure] (a) mode judgment routine new application program code (b) transfer routine
TMP1962F10AXBG tmp1962f-30 3.5 single boot mode in single boot mode, the flash memory can be re-programmed by using a program contained in the TMP1962F10AXBG on-chip boot rom. this boot rom is a masked rom. when single boot mode is selected upon reset, the boot rom is mapped to the addr ess region including the interrupt vector table while the flash memory is mapped to an address region different from it (see figure 3.3 on page 19). single boot mode allows for serial programming of the flash memory. channel 0 of the sio (sio0) of the TMP1962F10AXBG is connected to an external host controller. via this serial link, a programming routine is downloaded from the host controller to the TMP1962F10AXBG on-chip ram. then, the flash memory is re-programmed by executing the programming routine. the host sends out both commands and programming data to re-program the flash memory. communications between the sio0 and the host must follow the protocol described later. to secure the contents of the flash memory, the validity of the application?s password is checked before a programming routine is downloaded into the on-chip ram. if pass word matching fails, the transfer of a programming routine itself is aborted. as in the case of user boot mode, all interrupts including the nonmaskable (nmi) interrupt must be globally disabled in single boot mode while the flash memory is being erased or programmed. in single boot mode, the boot-rom programs are executed in normal mode. once re-programming is complete, it is recommended to protect relevant flash blocks from accidental corruption during subsequent single-chip (normal mode) operations. for a detailed description of the erase and program sequence, refer to 3.4 on-board programming and erasure.
TMP1962F10AXBG tmp1962f-31 (2-a) general procedure: using the program in the on-chip boot rom (1) the flash block containing the older version of the program code need not be erased before executing the programming routine. since a programming routine and programming data are transferred via the sio0, the sio0 must be connected to a ho st controller. prepare a programming routine on the host controller. (2) reset the TMP1962F10AXBG with the mode setting pi ns held at appropriate logic values, so that the cpu re-boots from the on-chip boot rom. the 12-byte password transferred from the host controller is first compared to the contents of special flash memory locations. (if the flash block has already been erased, th e password is 0xffff.) TMP1962F10AXBG flash memory ram old application program code (or erased state) host controlle r new application program code i/o (a) programming routine boot rom sio0 TMP1962F10AXBG host controlle r i/o 0 1 reset conditions for entering single boot mode new application program code (a) programming routine flash memory ram old application program code (or erased state) boot rom sio0 boot mode
TMP1962F10AXBG tmp1962f-32 (3) if the password was correct, the boot program do wnloads, via the sio0, the programming routine from the host controller into the on-chip ram of the TMP1962F10AXBG. the programming routine must be stored in the address range 0xfffd_6000 ? 0xfffd_efff. (4) the cpu jumps to the programming routine in the on-chip ram to erase the flash block containing the old application program code. the block erase or chip erase command may be used. TMP1962F10AXBG flash memory ram old application program code (or erased state) host controlle r new application program code i/o (a) programming routine boot rom sio0 (a) programming routine TMP1962F10AXBG flash memory ram host controlle r new application program code i/o (a) programming routine boot rom sio0 (a) programming routine erased
TMP1962F10AXBG tmp1962f-33 (5) next, the programming routine downloads new application program code from the host controller and programs it into the erased flash block. once programming is complete, protection of that flash block is turned on. it is not allowed to move program control from the programming routine back to the boot rom. in the example below, new program code comes from the same host controller via the same sio channel as for the programming routine. however, once the programming routine has begun to execute, it is free to change the tr ansfer path and the source of th e transfer. create board hardware and a programming routine to suit your particular needs. (6) when programming of the flash memory is comp lete, power off the board and disconnect the cable leading from the host to the targ et board. turn on the power ag ain so that the TMP1962F10AXBG re-boots in single-chip (normal) mode to execute the new program. TMP1962F10AXBG flash memory ram new application program code host controlle r new application program code i/o (a) programming routine boot rom sio0 (a) programming routine TMP1962F10AXBG host controlle r 0 1 reset set to single-chip (normal) mode flash memory ram new application program code boot rom sio0
TMP1962F10AXBG tmp1962f-34 3.5.1 host-to-target connection examples in single boot mode, serial transfer is used to re-program the flash memory while the TMP1962F10AXBG is installed on the board. in this mode, channel 0 of the sio (sio0) of the TMP1962F10AXBG is connected to a host controller, which is to issue commands to the target board. figure 3.6 and figure 3.7 show examples of host-to-target connections. figure 3.6 example of a connection betwee n a host controller and a target board (when the sio0 is configured for uart mode) target board txd0 (pc0) rxd0 (pc1) bw1 dvcc vcc pc rs232c rom mode control vcc vcc reg. 100 v a.c. host controller dvss reset tmode mcu mode control rx vss tx reset boot mode selection logic bw0 boot ram reg. nmi tmp1962
TMP1962F10AXBG tmp1962f-35 figure 3.7 example of a connection betwee n a host controller and a target board (when the sio0 is configured for i/o interface mode) target board txd0 (pc0) rxd0 (pc1) bw1 dvcc vcc pc rs232c rom mode control vcc vcc reg. 100 v a.c. host controller dvss reset tmode mcu mode control rx vss tx reset bw0 boot ram reg. nmi pi7 tbus y sclk0 (pc2) tck boot mode selection logic tmp1962
TMP1962F10AXBG tmp1962f-36 3.5.2 configuring for single boot mode for on-board programming, boot the TMP1962F10AXBG in single boot mode, as follows: bw0 = 1 bw1 = 1 boot = 0 reset = 0 1 set the reset input at logic 0, and the bw0, bw1 and boot (pj2) inputs at the logic values shown above, and then release reset (high). 3.5.3 memory map figure 3.8 shows a comparison of the memory maps in normal and single boot modes. in single boot mode, the on-chip flash memory is mapped to physical addresses (0x4000_0000 through 0x400f_ffff), virtual addresses (0x0000_0000 through 0x000f_ffff), and the on-chip boot rom is mapped to physical addresses 0x1fc0_0000 through 0x1fc0_1fff. figure 3.8 memory maps for normal and single boot modes (physical addresses) on-chip peripherals normal mode single boot mode 0x1fc0_1fff 0x1fc0_0000 0x0000_0000 0xffff_ffff 0xffff_e000 0xfffd_dfff 0xfffd_6000 0xff3f_ffff 0xff20_0000 0xc000_0000 0x400f_ffff 0x4000_0000 0x1fcf_ffff 0x1fc0_0400 0x1fc0_0000 0x2000_0000 0x0000_0000 0xff00_0000 0xbf00_0000 0xffff_ffff 0xffff_e000 0xfffd_dfff 0xfffd_6000 0xff3f_ffff 0xff20_0000 0xc000_0000 0x400f_ffff 0x4000_0000 0x2000_0000 0xff00_0000 0xbf00_0000 (reserved) on-chip ram (40 kb) (reserved) used for debugging (reserved) (reserved) (reserved) on-chip rom shadow inaccessible (512 mb) user program area maskable interrupt area exception vector area on-chip peripherals (reserved) on-chip ram (40 kb) (reserved) used for debugging (reserved) (reserved) (reserved) on-chip flash rom inaccessible (512 mb) boot rom (6 kb) internal rom
TMP1962F10AXBG tmp1962f-37 3.5.4 interface specification in single boot mode, an sio channel is used for communications with a programming controller. both uart (asynchronous) and i/o interface (synchronous) modes are supported. the communication formats are shown below. in the su bsections that follow, virtual addr esses are indicated, unless otherwise noted. ? uart mode communication channel: sio channel 0 (sio0) transfer mode: uart (asynchronous) mode, full-duplex data length: 8 bits parity bits: none stop bits: 1 baud rate: arbitrary baud rate ? i/o interface mode communication channel: sio channel 0 (sio0) transfer mode: i/o inte rface mode, half-duplex synchronization clock (sclk0): input handshaking signal: pi7 configured as an output baud rate: arbitrary baud rate table 3.4 required pin connections interface pin uart mode i/o interface mode dvcc2 (2.5 v) required required power supply pins dvss required required mode-setting pin boot required required reset pin reset required required txd0 required required rxd0 required required sclk0 not required required (input mode) communication pins p87 not required required (input mode) 3.5.5 data transfer format the host controller is to issue one of the commands listed in table 3.5 to the target board. table 3.6 to table 3.8 illustrate the sequence of two-way communications that should occur in response to each command. table 3.5 single boot mode commands code command 10h ram transfer 20h show flash memory sum 30h show product information
TMP1962F10AXBG tmp1962f-38 table 3.6 transfer format for the ram transfer command byte data transferred from the controller to the TMP1962F10AXBG baud rate data transferred from the TMP1962F10AXBG to the controller boot rom 1st byte serial operation mode and baud rate for uart mode 86h for i/o interface mode 30h desired baud rate (note 1) ? 2nd byte ? ack for the serial operation mode byte for uart mode normal acknowledge 86h (the boot program aborts if the baud rate is can not be set correctly.) for i/o interface mode normal acknowledge 30h 3rd byte command code (10h) ? 4th byte ? ack for the command code byte (note 2) normal acknowledge 10h negative acknowledge x1h communication error x8h 5th byte thru 16th byte password sequence (12 bytes) (0x4000_03f4 thru 0x4000_03ff) ? 17th byte checksum value for bytes 5?16 ? 18th byte ? ack for the checksum byte (note 2) normal acknowledge 10h negative acknowledge 11h communication error 18h 19th byte ram storage start address (bits 31?24) ? 20th byte ram storage start address (bits 23?16) ? 21st byte ram storage start address (bits 15?8) ? 22nd byte ram storage start address (bits 7?0) ? 23rd byte ram storage byte count (bits 15?8) ? 24th byte ram storage byte count (bits 7?0) ? 25th byte checksum value for bytes 19?24 ? 26th byte ? ack for the checksum byte (note 2) normal acknowledge 10h negative acknowledge 11h communication error 18h 27th byte thru mth byte ram storage data ? (m + 1)th byte checksum value for bytes 27?m ? (m + 2)th byte ? ack for the checksum byte (note 2) normal acknowledge 10h non-acknowledge 11h communications error 18h ram (m + 3)th byte ? jump to ram storage start address note 1: in i/o interface mode, the baud rate for the transfers of the first and second bytes must be 1/16 of the desired baud rate. note 2: in case of any negative acknowledge, the boot program returns to a state in which it waits for a command code (3rd byte). in i/o interface mode, if a communication error occurs, a negative acknowledge does not occur. note 3: the 19th to 25th bytes must be within the ram address range 0xfffd_6000?0xffff_dfff .
TMP1962F10AXBG tmp1962f-39 table 3.7 transfer format for the show flash memory sum command byte data transferred from the controller to the TMP1962F10AXBG baud rate data transferred from the TMP1962F10AXBG to the controller boot rom 1st byte serial operation mode and baud rate for uart mode 86h for i/o interface mode 30h desired baud rate (note 1) ? 2nd byte ? ack for the serial operation mode byte for uart mode normal acknowledge 86h (the boot program aborts if the baud rate can not be set correctly.) for i/o interface mode normal acknowledge 30h 3rd byte command code (20h) ? 4th byte ? ack for the command code byte (note 2) normal acknowledge 20h negative acknowledge x1h communication error x8h 5th byte ? sum (upper byte) 6th byte ? sum (lower byte) 7th byte ? checksum value for bytes 5 and 6 8th byte (wait for the next command code.) ? note 1: in i/o interface mode, the baud rate for the transfer s of the first and second bytes must be 1/16 of the desired baud rate. note 2: in case of any negative acknowledge, the boot program returns to a state in which it waits for a command code (3rd byte). in i/o interface mode, if a communication error occurs, a negative acknowledge does not occur.
TMP1962F10AXBG tmp1962f-40 table 3.8 transfer format for the show product information command (1/2) byte data transferred from the controller to the TMP1962F10AXBG baud rate data transferred from the TMP1962F10AXBG to the controller boot rom 1st byte serial operation mode and baud rate for uart mode 86h for i/o interface mode 30h ? 2nd byte ? desired baud rate (note 1) ack for the serial operation mode byte for uart mode normal acknowledge 86h (the boot program aborts if the baud rate can not be set correctly.) for i/o interface mode normal acknowledge 30h 3rd byte command code (30h) ? 4th byte ? ack for the command code byte (note 2) normal acknowledge 10h negative acknowledge x1h communication error x8h 5th byte ? flash memory data (at address 0x4000_03f0h) 6th byte ? flash memory data (at address 0x4000_03f1h) 7th byte ? flash memory data (at address 0x4000_03f2h) 8th byte ? flash memory data (at address 0x4000_03f3h) 9th byte thru 20th byte ? product name (12-byte ascii code) ?tx1962f10? from the 9th byte 21st byte thru 24th byte ? password comparison start address (4 bytes) f4h, 03h, 00h and 00h from the 21st byte 25th byte thru 28th byte ? ram start address (4 bytes) 00h, 60h, fdh and ffh from the 25th byte 29th byte thru 32nd byte ? dummy data (4 bytes) ffh, 6fh, fdh and ffh from the 29th byte 33rd byte thru 36th byte ? ram end address (4 bytes) ffh, dfh, fdh and ffh from the 33rd byte 37th byte thru 40th byte ? dummy data (4 bytes) 00h, 70h, fdh and ffh from the 37th byte 41st byte thru 44th byte ? dummy data (4 bytes) ffh, efh, fdh and ffh from the 41st byte 45th byte thru 46th byte ? fuse information (2 bytes) 01h and 00h from the 45th byte 47th byte thru 50th byte ? flash memory start address (4 bytes) 00h, 00h, 00h and 00h from the 47th byte 51st byte thru 54th byte ? flash memory end address (4 bytes) ffh, ffh, 0fh and 00h from the 51st byte 55th byte thru 56th byte ? flash memory block count (2 bytes) 08h and 00h from at the 55th byte
TMP1962F10AXBG tmp1962f-41 table 3.8 transfer format for the show product information command (2/2) byte data transferred from the controller to the TMP1962F10AXBG baud rate data transferred from the TMP1962F10AXBG to the controller 57th byte thru 60th byte ? start address of a group of the same-size flash blocks (4 bytes) 00h, 00h, 00h and 00h from the 57th byte boot rom 61st byte thru 64th byte ? size (in halfwords) of the same-size flash blocks (4 bytes) 00h, 00h, 01h and 00h from the 61st byte 65th byte ? number of flash blocks of the same size (1 byte) 08h 66th byte ? checksum value for bytes 5 to 65 67th byte (wait for the next command code.) ? 3.5.6 overview of the boot program commands when single boot mode is selected, the boot program is automatically executed on startup. the boot program offers these three commands, the details of which are provided on the following subsections. ? ram transfer command the ram transfer command stores program code transferred from a host controller to the on-chip ram and executes the program once the transfer is successfully completed. the maximum program size is 36 kbytes. the ram storage start address must be within the range. the ram transfer command can be used to download a flash programming routine of your own; this provides the ability to control on-board programming of the flash memory in a unique manner. the programming routine must utilize the flash memory command sequences described in section 3.6.17 before initiating a transfer, th e ram transfer command checks a password sequence coming from the controller against that stored in the flash memory. if they do not match, the ram transfer command aborts. once the ram transfer command is complete, the whole on-chip ram is accessible. ? show flash memory sum command the show flash memory sum command adds the contents of the 1024 kbytes of the flash memory together. the boot program does not provide a command to read out the contents of the flash memory. instead, the flash memory sum command can be used for software revision management. ? show product information command the show product information command provides the product name, on-chip memory configuration and the like. this command also reads out the contents of the flash memory locations at addresses 0x0000_03f0 through 0x0000_03f3. in addition to the show flash memory sum command, these locations can be used for software revision management. note 1: in i/o interface mode, the baud rate for the transfers of the first and second bytes must be 1/16 of the desired baud rate. note 2: in case of any negative acknowledge, the boot program returns to a state in which it waits for a command code (3rd byte). in i/o interface mode, if a communication error occurs, a negative acknowledge does not occur.
TMP1962F10AXBG tmp1962f-42 3.5.7 ram transfer command see table 3.6. (1) the 1st byte specifies which one of the two serial operation modes is used. for a detailed description of how the serial operation mode is determined, see section 3.5.11. if it is determined as uart mode, the boot program then checks if the sio0 is programmable to the baud rate at which the 1st byte was transferred. during the first-byte interv al, the rxe bit in the sc0m od register is cleared. ? to communicate in uart mode send, from the controller to the target board, 86h in uart data format at the desired baud rate. if the serial operation mode is determined as uart, then the boot progr am checks if the sio0 can be programmed to the baud rate at which the first byte was transferred. if that baud rate is not possible, the boot program aborts, disabling any subsequent communications. ? to communicate in i/o interface mode send, from the controller to the target board, 30 h in i/o interface data format at 1/16 of the desired baud rate. also send the 2nd byte at the same baud rate. then send all subsequent bytes at a rate equal to the desired baud rate. in i/o interface mode, the cpu sees the serial r eceive pin as if it were a general input port in monitoring its logic transitions. if the baud rate of the incoming data is high or the chip?s operating frequency ishigh, the cpu may not be able to keep up with the speed of logic transitions. to prevent such situations, the 1st a nd 2nd bytes must be transferred at 1/16 of the desired baud rate; then the boot program calculates 16 times that as the desired baud rate. when the serial operation mode is determined as i/o interface mode, the sio0 is configured for sclk input mode. beginning with the third byte, the controller must ensure that its ac timing restrictions are satisfied at the selected baud rate. in the case of i/o interface mode, the boot program does not check the receive error flag; thus there is no su ch thing as error acknowledge (x8h). (2) the 2nd byte, transmitted from the target board to the controller, is an acknowledge response to the 1st byte. the boot program echoes back the first byte: 86h for uart mode and 30h for i/o interface mode. ? uart mode if the sio0 can be programmed to the baud rate at which the 1st byte was transferred, the boot program programs the br0cr and sends back 86h to the controller as an acknowledge. if the sio0 is not programmable at that baud rate, the boot program simply aborts with no error indication. following the 1st byte, the controller should allow for a time-out period of five seconds. if it does not receive 86h within th e alloted time-out period, the controller should give up the communication. the boot program sets the rxe bit in the sc0mod register to enable reception before loading the sio transmit buffer with 86h.
TMP1962F10AXBG tmp1962f-43 ? i/o interface mode the boot program programs the sc0mod0 and sc0cr registers to configure the sio0 in i/o interface mode (clocked by the rising edge of sclk0), writes 30h to the sc0buf. then, the sio0 waits for the sclk0 signal to come from the controller. following the transmission of the 1st byte, the controller should send the sclk clock to the target board after a certain idle time (several microseconds). this must be done at 1/16 the desire baud rate. if the 2nd byte, which is from the target board to the controller, is 30h, then the controller should take it as a go-ahead. the controller must then delivers the 3rd byte to the target board at a rate equal to the desired baud rate. the boot program sets the rxe bit in the sc0mod register to enable reception before loading the sio transmit buffer with 30h. (3) the 3rd byte, which the target board receives from the controller, is a command. the code for the ram transfer command is 10h. (4) the 4th byte, transmitted from the target board to the controller, is an acknowledge response to the 3rd byte. before sending back the acknowledge response, the boot program checks for a receive error. if there was a receive error, the boot program transmits x8h and returns to the state in which it waits for a command again. in this case, the upper four bits of the acknowledge response are undefined ? they hold the same values as the upper four bits of the previously issued command. when the sio0 is config ured for i/o interface mode, the boot program does not check for a receive error. if the 3rd byte is equal to any of the command codes listed in table 3.5, the boot program echoes it back to the controller. when the ram transfer command was r eceived, the boot program echoes back a value of 10h and then bran ches to the ram transfer routine. once this branch is taken, a password check is done. password checking is detailed in section 3.5.12. if the 3rd byte is not a valid command, the boot program sends back x1h to the controller and returns to the state in which it waits for a command again. in this case, the upper four bits of the acknowledge response are undefined ? they hold the same values as the upper four bits of the previously issued command. (5) the 5th to 16th bytes, which the target board r eceives from the controller, are a 12-byte password. the 5th byte is compared to the contents of ad dress 0x0000_03f4 in the flash memory; the 6th byte is compared to the contents of address 0x0000_03f5 in the flash memory; likewise, the 16th byte is compared to the contents of address 0x0000_03ff in the flash memory. if the password checking fails, the ram transfer routine sets the password error flag. (6) the 17th byte is a checksum value for the password sequence (5th to 16th bytes). to calculate the checksum value for the 12-byte passw ord, add the 12 bytes together, drop the carries and take the two?s complement of the total sum. transmit this checksum value from the controller to the target board. the checksum calculation is described in details in section 3.5.14.
TMP1962F10AXBG tmp1962f-44 (7) the 18th byte, transmitted from the target board to the controller, is an acknowledge response to the 5th to 17th bytes. first, the ram transfer routine ch ecks for a receive error in the 5t h to 17th bytes. if there was a receive error, the boot program sends back 18h and returns to the state in which it waits for a command (i.e., the 3rd byte) again. in this case, the upper four bits of the acknowledge response are the same as those of the previously issued command (i.e., all 1s). when the sio0 is configured for i/o interface mode, the ram transfer routin e does not check fo r a receive error. next, the ram transfer routine performs the chec ksum operation to ensure data integrity. adding the series of the 5th to 17th bytes must result in zero (with the carry dropped). if it is not zero, one or more bytes of data has been corrupted. in case of a checksum error, the ra m transfer routine sends back 11h to the controller and retu rns to the state in which it waits for a command (i.e., the 3rd byte) again. finally, the ram transfer routine examines the result of the password check. the following two cases are treated as a password error. in these cases, the ram transfer r outine sends back 11h to the controller and returns to the state in which it waits for a command (i.e., the 3rd byte) again. ? irrespective of the result of the password comparison, all of the 12 bytes of a password in the flash memory are the same value other than ffh. ? not all of the password bytes transmitted from the controller matched those contained in the flash memory. when all the above checks have been successful , the ram transfer rou tine returns a normal acknowledge response (10h) to the controller. (8) the 19th to 22nd bytes, which th e target board receives from the c ontroller, indicate the start address of the ram region where subsequent data (e.g., a flash programming routine) should be stored. the 19th byte corresponds to bits 31?24 of the address, and the 22nd byte corresponds to bits 7?0 of the address. (9) the 23rd and 24th bytes, whic h the target board receives from th e controller, indicate the number of bytes that will be transferred from the controller to be stored in the ram. the 23rd byte corresponds to bits 15?8 of the number of bytes to be transferred, and the 24th byte corresponds to bits 7?0 of the number of bytes. (10) the 25th byte is a checksum value for the 19th to 24th bytes. to calculate the checksum value, add all these bytes together, drop the carries and take the two?s complement of the total sum. transmit this checksum value from the controller to the ta rget board. the checksum calculation is described in details in section 3.5.14. (11) the 26th byte, transmitted from the target board to the controller, is an acknowledge response to the 19th to 25th bytes of data. first, the ram transfer ro utine checks for a receive error in th e 19th to 25th bytes. if there was a receive error, the ram transfer r outine sends back 18h and returns to the state in which it waits for a command (i.e., the 3rd byte) again. in this case, the upper four bits of the acknowledge response are the same as those of the previously issued co mmand (i.e., all 1s). when the sio0 is configured for i/o interface mode, the ram transfer routine does not check for a receive error. next, the ram transfer routine performs the chec ksum operation to ensure data integrity. adding the series of the 19th to 25th bytes must result in zero (with the carry dropped). if it is not zero, one or more bytes of data has been corrupted. in case of a checksum error, the ram transfer routine sends back 11h to the controller and returns to the state in which it waits for a command (i.e., the 3rd byte) again.
TMP1962F10AXBG tmp1962f-45 ? the ram storage start address must be within the range 0xfffd_6000?0xfffd_efff. when the above checks have been successful, the ram transfer rou tine returns a normal acknowledge response (10h) to the controller. (12) the 27th to mth bytes from the controller are stored in the on-chip ram of the TMP1962F10AXBG. storage begins at the address specified by the 19th?22nd bytes and continues for the number of bytes specified by the 23rd?24th bytes. (13) the (m+1)th byte is a checksum value. to calc ulate the checksum value, ad d the 27th to mth bytes together, drop the carries and take the two?s complement of the total sum. transmit this checksum value from the controller to the target board. the checksum calculation is described in details in section 3.5.14. (14) the (m+2)th byte is a acknowledge response to the 27th to (m+1)th bytes. first, the ram transfer routine ch ecks for a receive error in the 27th to (m+1)t h bytes. if there was a receive error, the ram transfer routine sends back 18h and returns to the state in which it waits for a command (i.e., the 3rd byte) again. in this cas e, the upper four bits of the acknowledge response are the same as those of the previously issued co mmand (i.e., all 1s). when the sio0 is configured for i/o interface mode, the ram transfer routine does not check for a receive error. (15) next, the ram transfer routine performs the checksum operation to ensure data integrity. adding the series of the 27th to (m+1)th bytes must result in zero (with the carry dropped). if it is not zero, one or more bytes of data has been corrupted. in case of a checksum error, the ram transfer routine sends back 11h to the controller and returns to the state in which it waits for a command (i.e., the 3rd byte) again. when the above checks have been successful, the ram tran sfer routine returns a normal acknowledge response (10h) to the controller. if the (m+2)th byte was a normal acknowledge response, a branch is made to the addres s specified by the 19th to 22nd bytes in 32-bit isa mode. 3.5.8 show flash memory sum command see table 3.7. (1) the processing of the 1st and 2nd bytes are the same as for the ram transfer command. (2) the 3rd byte, which the target board receives fr om the controller, is a command. the code for the show flash memory sum command is 20h. (3) the 4th byte, transmitted from the target board to the controller, is an acknowledge response to the 3rd byte. before sending back the acknowledge response, the boot program checks for a receive error. if there was a receive error, the boot progra m transmits x8h and returns to the state in which it waits for a command again. in this case, the upper four bits of the acknowledge response are undefined ? they hold the same values as the upper four bits of the previously issued command. when the sio0 is config ured for i/o interface mode, the boot program does not check for a receive error. if the 3rd byte is equal to any of the command codes listed in table 3.5 on page 37, the boot program echoes it back to the controller. when the sh ow flash memory sum command was received, the boot program echoes back a value of 20h and then branches to the show flash memory sum routine. if the 3rd byte is not a valid command, the boot program sends back x1h to the controller and returns
TMP1962F10AXBG tmp1962f-46 to the state in which it waits for a command again. in this case, the upper four bits of the acknowledge response are undefined ? they hold the same values as the upper four bits of the previously issued command. (4) the show flash memory sum routine adds all the bytes of the flash memory together. the 5th and 6th bytes, transmitted from the target board to the controller, indicate the upper and lower bytes of this total sum, respectively. for details on sum calculation, see section 3.5.13. (5) the 7th byte is a checksum value for the 5th and 6th bytes. to calculate the checksum value, add the 5th and 6th bytes together, drop the carry and take the two?s complement of the sum. transmit this checksum value from the controller to the target board. (6) the 8th byte is the next command code. 3.5.9 show product information command see table 3.8. (1) the processing of the 1st and 2nd bytes are the same as for the ram transfer command. (2) the 3rd byte, which the target board receives fr om the controller, is a command. the code for the show product information command is 30h. (3) the 4th byte, transmitted from the target board to the controller, is an acknowledge response to the 3rd byte. before sending back the acknowledge response, the boot program checks for a receive error. if there was a receive error, the boot progra m transmits x8h and returns to the state in which it waits for a command again. in this case, the upper four bits of the acknowledge response are undefined ? they hold the same values as the upper four bits of the previously issued command. when the sio0 is config ured for i/o interface mode, the boot program does not check for a receive error. if the 3rd byte is equal to any of the command codes listed in table 3.5 on page 37, the boot program echoes it back to the controller. when the show flash memory sum command was received, the boot program echoes back a value of 30h and then branches to the show flash memory sum routine. if the 3rd byte is not a valid command, the boot program sends back x1h to the controller and returns to the state in which it waits for a command again. in this case, the upper four bits of the acknowledge response are undefined ? they hold the same values as the upper four bits of the previously issued command. (4) the 5th to 8th bytes, transmitted from the target board to the controller, are the data read from addresses 0x0000_03f0?0x0000_03f3 in the flash memory. software version management is possible by storing a software id in these locations. (5) the 9th to 20th bytes, transmitted from the target board to the controller, indicate the product name, which is ?tx1962f10___? in asci i code (where _ is a space).
TMP1962F10AXBG tmp1962f-47 (6) the 21st to 24th bytes, transmitted from the target board to the controller, indicate the start address of the flash memory area containing th e password, i.e., f4h, 03h, 00h, 00h. (7) the 25th to 28th bytes, transmitted from the target board to the controller, indicate the start address of the on-chip ram, i.e., 00h, 60h, fdh, ffh. (8) the 29th to 32nd bytes, transmitted from the ta rget board to the controller, are dummy data (ffh, 6fh, fdh, ffh). (9) the 33rd to 36th bytes, transmitted from the target board to the controller, indicate the end address of the on-chip ram, i.e., ffh, ffh, fdh, ffh. (10) the 37th to 40th bytes, transmitted from the ta rget board to the controller, are 00h, 70h, fdh and ffh. the 41st to 44th bytes, transmitted from the target board to the controller, are ffh, efh, fdh and ffh. (11) the 45th and 46th bytes, transmitted from the ta rget board to the controlle r, indicate the presence or absence of the security and protect bits and whether the flash memory is divided into blocks. bit 0 indicates the presence or absence of the security b it; it is 0 if the security bit is available. bit 1 indicates the presence or absence of th e protect bits; it is 0 if the protect bits are available. if bit 2 is 0, it indicates that the flash memory is divided into blocks. the remaining bits are undefined. the 45th and 46th bytes are 01h, 00h. (12) the 47th to 50th bytes, transmitted from the target board to the controller, indicate the start address of the on-chip flash memory, i.e., 00h, 00h, 00h, 00h. (13) the 51st to 54th bytes, transmitted from the target board to the controller, indicate the end address of the on-chip flash memory, i.e., ffh, ffh, 0fh, 00h. (14) the 55th to 56th bytes, transmitted from the target board to the controller, indicate the number of flash blocks available, i.e., 08h, 00h. (15) the 57th to 92nd bytes, transmitted from the target board to the controller, contain information about the flash blocks. flash blocks of the same size are treated as a grou p. information about the flash blocks indicate the start address of a group, the size of the blocks in that group (in halfwords) and the number of the blocks in that group. the 57th to 65th bytes are the information about the 128-kbyte blocks (block 0 to block 7). see table 3.8 for the values of bytes transmitted. (16) the 66th byte, transmitted from the target board to the controller, is a checksum value for the 5th to 65th bytes. the checksum value is calculated by adding all these bytes together, dropping the carry and taking the two?s complement of the total sum. (17) the 67th byte is the next command code.
TMP1962F10AXBG tmp1962f-48 3.5.10 acknowledge responses the boot program represents processing states with specific codes. table 3.9 to table 3.11 show the values of possible acknowledge responses to the recei ved data. the upper four bits of the acknowledge response are equal to those of the command being execut ed. bit 3 of the code indicates a receive error. bit 0 indicates an invalid command error, a checksum error or a password error. bit 1 and bit 2 are always 0. receive error checking is not done in i/o interface mode. table 3.9 ack response to the serial operation mode byte return value meaning 86h the sio can be configured to operate in uart mode. (see note) 30h the sio can be configured to operate in i/o interface mode. table 3.10 ack response to the command byte return value meaning x8h (see note) a receive error occurred while getting a command code. x1h (see note) an undefined command code was received. (reception was completed normally.) 10h the ram transfer command was received. 20h the show flash memory sum command was received. 30h the show product information command was received. table 3.11 ack response to the checksum byte return value meaning 18h a receive error occurred. 11h a checksum or password error occurred. 10h the checksum was correct. note: if the serial operation mode is determined as uart, the boot program checks if the sio can be programmed to the baud rate at which the operation mode byte was transferred. if that baud rate is not possible, the boot program aborts, without sending back any response. note: the upper four bits of the ack response are the same as those of the previous command code.
TMP1962F10AXBG tmp1962f-49 3.5.11 determination of a serial operation mode the first byte from the controller determines the serial operation mode. to use uart mode for communications between the controller and the target board, the controller must first send a value of 86h at a desired baud rate to the target board. to use i/o interface mode, the controller must send a value of 30h at 1/16 the desired baud rate. figure 3.9 shows the waveforms for the first byte. figure 3.9 serial operation mode byte after reset is released, the boot program monitors the first serial byte from the controller, with the sio reception disabled, and calculates the intervals of tab, tac and tad. figure 3.10 shows a flowchart describing the steps to determine the intervals of ta b, tac and tad. as shown in the flowchart, the boot program captures timer counts each time a logic transition occurs in th e first serial byte. consequently, the calculated tab, tac and tad intervals are bound to have slight errors. if the transfer goes at a high baud rate, the cpu might not be able to keep up with the spee d of logic transitions at th e serial receive pin. in particular, i/o interface mode is more prone to this problem since its baud rate is generally much higher than that for uart mode. to avoid such a situation, the controller should send the first serial byte at 1/16 the desired baud rate. the flowchart in figure 3.11 shows how the boot program distinguishes between uart and i/o interface modes. if the length of tab is equal to or less than the length of tcd, the serial operation mode is determined as uart mode. if the legnth of tab is greater than the length of tcd, the serial operation mode is determined as i/o interface mode. bear in mi nd that if the baud rate is too high or the timer operating frequency is too low, the timer resolution will be coarse, relative to the intervals between logic transitions. this becomes a problem due to inherent errors caused by the way in which timer counts are captured by software; consequently the boot program might not be able to determine the serial operation mode correctly. for example, the serial operation mode may be dete rmined to be i/o interface mode when the intended mode is uart mode. to avoid such a situation, when uart mode is utilized, the controller should allow for a time-out period within which it expects to recei ve an echo-back (86h) from the target board. the controller should give up the communication if it fails to get that echo-back within the alloted time. when i/o interface mode is utilized, once the first serial byte has been transmitted, the controller should send the sclk clock after a certain idle time to get an acknowledge response. if the received acknowledge response is not 30h, the controller should give up further communications. uart (86h) tab point a point b point c point d bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 start stop tcd i/o interface (30h) tab bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 tcd point a point b point c point d
TMP1962F10AXBG tmp1962f-50 figure 3.10 serial operation mode byte reception flow initialize 16-bit timer 0 ( t1 = 8/fc, counter cleared) set tb0rg1 to 0xffff prescaler is on. 16-bit timer 0 starts counting up point a stop operation (infinite loop) high-to-low transition on serial receive pin? yes yes yes start low-to-high transition on serial receive pin? software-capture and save timer value (tab) high-to-low transition on serial receive pin? software-capture and save timer value (tac) yes low-to-high transition on serial receive pin? software-ca p ture and save timer value ( tad ) 16-bit timer 0 stops counting tac tad? make backup copy of tad value done yes point b point c point d
TMP1962F10AXBG tmp1962f-51 figure 3.11 serial operation mode determination flow 3.5.12 password the ram transfer command (10h) causes the boot program to perform a password check. following an echo-back of the command code, the boot program checks the contents of the 12-byte password area (0x4000_03f4 to 0x4000_03ff) within the flash memory. if all these address locations contain the same bytes of data other than ffh, a password area error occurs. in this case, the boot program returns an error acknowledge (11h) in response to the checksum byte (the 17th byte), regardless of whether the password sequence sent from the controller is all ffhs. the password sequence received from the controller (5th to 16th bytes) is compared to the password stored in the flash memory. table 3.12 shows how they are compared byte-by-byte. all of the 12 bytes must match to pass the password check. otherwise, a password error occurs, which causes the boot program to return an error acknowledge in response to the checksum byte (the 17th byte). figure 3.12 password area check flow tcd tad ? tac tab > tcd? start yes uart mode i/o interface mode are all bytes equal to ffh? start yes password area error are all bytes the same? password area is normal. yes no no
TMP1962F10AXBG tmp1962f-52 table 3.12 relationship between received bytes and flash memory locations received byte compared flash memory data 5th byte address 0x0000_03f4 6th byte address 0x0000_03f5 7th byte address 0x0000_03f6 8th byte address 0x0000_03f7 9th byte address 0x0000_03f8 10th byte address 0x0000_03f9 11th byte address 0x0000_03fa 12th byte address 0x0000_03fb 13th byte address 0x0000_03fc 14th byte address 0x0000_03fd 15th byte address 0x0000_03fe 16th byte address 0x0000_03ff 3.5.13 calculation of the show flash memory sum command the show flash memory sum command adds all 1024 kbytes of the flash memory together and provides the total sum as a halfword quantity. the sum is sent to the controller, with the upper eight bits first, followed by the lower eight bits. example: 3.5.14 checksum calculation the checksum byte for a series of bytes of data is calculated by adding the byt es together, dropping the carries, and taking the two?s complement of the to tal sum. the show flash memory sum command and the show product information command perform the checksum calculation. the controller must perform the same checksum operation in transmitting checksum bytes. example: assume the show flash memory sum command provides the upper and lower bytes of the sum as e5h and f6h. to calculate the checksum for a series of e5h and f6h: (1) add the bytes together. e5h + f6h = 1dbh (2) drop the carry. (3) take the two?s complement of the sum, and that is the checksum byte. 0 ? dbh = 25h a1h b2h c3h d4h for the interest of simplicity, assume the depth of the flash memory is four locations. then the sum of the four bytes is calculated as: a1h + b2h + c3h + d4h = 02eah hence, 02h is first sent to the controller, followed by eah.
TMP1962F10AXBG tmp1962f-53 3.5.15 general boot program flowchart figure 3.13 shows an overall flowchart of the boot program. figure 3.13 overall boot program flow initialize i/o interface single boot program starts get sio operation mode data sio operation mode? set i/o interface mode ack data received data (30h) (send 30h) normal response prepare to get a command receive routine get a command ack data ack data & 0xf0 no normally receive error? ram transfer? ack data received data (10h) transmission routine (send 10h: normal response) yes (10h) ram transfer processing processed normall y ? jump to ram yes normally baud rate settin g ? program uart mode and baud rate ack data received data (86h) (send 86h) normal response ack data ack data 0x08 stop operation uart cannot be set transmission routine (send x8h: receive error) show flash memory sum? show product information? command error yes (20h) yes (30h) ack data received data (20h) ack data received data (30h) ack data ack data | 0x01 transmission routine (send 20h: normal response) transmission routine (send 30h: normal response) transmission routine (send x1h: command error) show flash memory sum processing show product information processing yes can be set
TMP1962F10AXBG tmp1962f-54 3. 3.6 on-board programming and erasure the TMP1962F10AXBG flash memory is command set compatible with the jedec eeprom standard, with a few exceptions. in user boot mode and single boot mode (the ram transfer command), the flash memory can be programmed and erased by the cp u executing software commands. it is the user?s responsibility to create a program/erase routine. because the flash memory can not be read while it is being programmed or erased, the program/erase routine must be executed out of the on-ch ip ram or an external memory device. 3.6.1 key features the TMP1962F10AXBG flash memory commands are in principle compatible with the standard jedec commands. for program/erase operations, the sy stem can issue a command sequence to the flash memory by using cpu instructions such as ld. after the command sequence is written, the flash memory does not require the system to provide further controls or timings. the flash memory initiates the embedded program or erase algorithm automatically. the entire flash memory or one or more flash blocks can be erased at a time. table 3.14 flash memory features feature description auto program programs and verifies the desir ed addresses word by word automatically. auto chip erase erases and verifies the entire memory array automatically. auto block erase erases and verifies all memory locations in the selected block automatically. auto multi-block erase erases and verifies all memory locations in multiple selected blocks automatically. write operation status provides several status bits su ch as the data polling bit and toggle bit, which can be used to determine whether a program or eras e operation is complete or in progress. security feature prevents intrusive access to t he flash memory while in programmer mode. when the security feature is turned off, the entire memory array is erased and verified automatically, regardless of whether a given block is protected or not. block protection disables both program and erase operations in any block. bear in mind that, due to the on-chip cpu interface, the tmp1962f 10axbg uses addr esses different from those of the standard flash command sequences . unless otherwise noted, programming is done word by word; thus the word load instruction should be used to write to the flash array.
TMP1962F10AXBG tmp1962f-55 3.6.2 block architecture 0xxxxx_0000 128 kbytes 128 kbytes 128 kbytes 128 kbytes 128 kbytes 128 kbytes 128 kbytes 128 kbytes 128 kbytes 128 kbytes 128 kbytes 128 kbytes 128 kbytes 128 kbytes 128 kbytes 128 kbytes 128 kbytes 128 kbytes 0xxxxf_ffff 128 kbytes x: depends on the TMP1962F10AXBG operation mode figure 3.16 flash memory block architecture 3.6.3 cpu-to-flash interface figure 3.17 illustrates the internal interface between the cpu and the flash memory in on-board programming modes. the diagram does not show the actual logic network; instead it is only a conceptual depiction of the cpu-to-flash interface. figure 3.17 internal cpu-to-flash interface single-chip mode: 0x1fc0_0000 ? 0x1fcf_ffff (physical address) single boot mode: 0x4000_0000 ? 0x400f_ffff (physical address) decoder operation m ode flash memory dq31 ? dq0 d31 ? d0 a31 ? a17 a16 ? a2 a d14 ? ad0 cpu ce we oe wr rd rdy_ bsy reset cpu reset (1024 kb) register
TMP1962F10AXBG tmp1962f-56 3.6.4 read mode and embedded operation mode the flash memory of the TMP1962F10AXBG has the following two modes of operation: ? read mode in which array data is read ? embedded operation mode in which the flash array is programmed or erased the flash memory enters embedded operation mode when a valid command sequence is executed in read mode. in embedded operation mode, array data can not be read. 3.6.5 reading array data the flash memory is automatically set to readi ng array data upon cpu reset after device power-up and after an embedded operation is successfully complete d. if an embedded operation terminated abnormally or the flash memory is required to return to the r ead mode, the read/reset co mmand (software reset) or hardware reset is used. 3.6.6 writing commands the operations of the flash memory are selected by commands or command sequences written into the internal command register. this uses the same mechanism as for jedec-standard eeproms. commands are made up of data sequences written at specific addresses via the command register. see table 3.16 on page 63 for the list of command sequences. the command sequence being written can be canceled by issuing the read/reset command between sequence cycles. the read/reset command clears the co mmand register and resets the flash memory to read mode. invalid command sequences also cause th e flash memory to clear the command register and return to read mode. 3.6.7 reset ? read/reset command (software reset) the flash memory does not return to read mode if an embedded operation terminated abnormally. in this case, the read/reset command must be issued to put the flash memory back in read mode. the read/reset command may also be written between sequence cycles of the command being written to clear the command register. ? hardware reset ( reset input) as shown in figure 3.17, the flash memory has a reset pin, which is connected to the reset signal of the cpu. when the system drives the reset pin to v il or when certain events such as a watchdog timer time-out causes a cpu reset, the flash memory immediately terminates any operation in progress and is reset to read mode. the read/reset command is also tied to the reset pin to reset the flash memory to read mode. the embedded operation that was interrupted should be re-initia ted once the flash memory is ready to accept another command sequen ce because data may be corrupted. for a description of the hardware reset operation, see section 3.3.2, reset operation . when a valid reset is achieved, the cpu reads the re set exception vector from the flash memory and services the reset exception.
TMP1962F10AXBG tmp1962f-57 3.6.8 auto program command a bit must be programmed to change its state from a 1 to a 0. a bit can not be programmed from a 0 back to a 1. only an erase opera tion can change a 0 back to a 1. in user boot mode and the ram transfer command of single boot mode, the auto program command programs the desired addresses word by word. the auto program command requires four bus cycles; the program address and data are written in the four th cycle, upon completion of which the program operation will commence. as programming is performed on a word-by-word basis, the program address must be a multiple of four. writing data shorter than a 32-bit word requires special considerations for the bits that are not to be altered. the word in the memory does not need to be in the erased state prior to programming. if the word is in the erased state, a 32-bit write must be performed, with all the bits not to be altered set to 1. examples: ? when a word location is in the erased state to program the least-significant byte of that word to 55h, 0xffff_ff55 must be written to the word address. note : the superscription of data cannot be done in the flash memory. the auto program command executes a sequence of internally timed events to program the desired bits of the addressed memory word and verify that the desired bits are sufficiently programmed. the system can determine the status of the programming operation by using write status flags (see table 3.19 on page 65). any commands written during the programming operati on are ignored. a hardware reset immediately terminates the programming operation. the progra mming operation that was interrupted should be re-initiated once the flash memory is ready to accept another command sequence because data may be corrupted. the block protection feature disables programming opera tions in any block. if an attempt is made to program a protected block, the auto program command does nothing; the flash memory returns to read mode in approximately 3 m after the completion of the fourth bus cycle of the command sequence. when the embedded auto program algorithm is complete, the flash memory returns to read mode. if any failure occurs during the programming operation, the flash memory remains locked in embedded operation mode. the system can determine this status by using write status flags. to put the flash memory back in read mode, use the read/reset command to reset the flash memory or a hardware reset to reset the whole chip. in case of a progra mming failure, it is recommended to replace the chip or discontinue the use of the failing flash block. 3.6.9 auto chip erase command the auto chip erase command requires six bus cycles. the flash area is partitioned into two areas, that are block 0 to block 3 (flash 0) and block 4 to bloc k 7 (flash 1). the chip erase operation is performed for individual area. set a[19] (addre ss 19) = 0 for flash 0, and a[19] = 1 for flash 1 by each bus cycle. after completion of the sixth bus cycle, the auto chip erase operation will commence immediately. the embedded auto chip erase algorithm automatically pr eprograms the entire memory for an all-0 data pattern prior to the erase; then it automatically eras es and verifies the entire memory for an all-1 data pattern. the system can determine the status of the chip erase operation by using write status flags (see
TMP1962F10AXBG tmp1962f-58 table 3.19 on page 65). any commands written during the chip erase operati on are ignored. a hardwa re reset immediately terminates the chip erase operation. the chip erase operation that was interrupted should be re-initiated once the flash memory is ready to accept another command sequence because data may be corrupted. the block protection feature disables erase operations in any block. the auto chip erase algorithm erases the unprotected blocks and ignores the protected blocks. if all the blocks are protected, the auto chip erase command does nothing; the flash memory returns to read mode in approximately 100 m after the completion of the sixth bus cycle of the command sequence. when the embedded auto chip erase algorithm is complete, the flash memory returns to read mode. if any failure occurs during the erase operation, the flash memory remains locked in embedded operation mode. the system can determine this status by using write status flags. to put the flash memory back in read mode, use the read/reset comma nd to reset the flash memory or a hardware reset to reset the whole chip. in case of an erase failure, it is recommended to replace the chip or discontinue the use of the failing flash block. the failing block can be identified by means of the block erase command. 3.6.10 auto block erase and auto multi-block erase commands the auto block erase command requires six bus cycles. a time-out begins from the completion of the command sequence. after a time-out, the erase operation will commence. the embedded auto block erase algorithm automatically preprogr ams the selected block for an all- 0 data pattern, and then erases and verifies that block for an all-1 data pattern. during the time-out period, additional block addr esses and auto block erase commands may be written. multi-block is selectable in either flash 0 area or flash 1 area. any command other than auto block erase during the time-out period resets the flash memory to read mode. the block erase time-out period is 50 m. the system may read dq3 to determine whether the time-out period has expired. the block erase timer begins counting upon completion of the sixth bus cycle of the auto block erase command sequence. th e system can determine the status of the erase operation by using write status flags (see table 3.19 on page 65). any commands written during the block erase operati on are ignored. a hardwa re reset immediately terminates the block erase operation. the block erase operation that was interrupt ed should be re-initiated once the flash memory is ready to accept another command sequence because data may be corrupted. the block protection feature disables erase operations in any block. the auto block erase algorithm erases the unprotected blocks and ignores the protected blocks. if all the selected blocks are protected, the auto block erase algorithm does nothing; the flash memory returns to read mode in approximately 100 m after the final bus cycle of the command sequen ce. when the embedded auto block erase algorithm is complete, the flash memory returns to read mode. if any failure occurs during the erase operation, the flash memory remains locked in embedded operation mode. the system can determine this status by using write status flags. to put the flash memory back in read mode, use the read/reset comma nd to reset the flash memory or a hardware reset to reset the whole chip. in case of an erase failure, it is recommended to replace the chip or discontinue the use of the failing flash block. if any failure occurred during the multi-block erase operation, the failing block can be identified by running auto block erase on each of the blocks selected for multi-block erasure.
TMP1962F10AXBG tmp1962f-59 3.6.11 block protect command the block protection feature disables both progr am and erase operations in any block. after completion of the seventh bus write cycle, fcls is 0 during block protect operation, and 1 after block protect operation. table 3.15 effects of the program and erase commands on the protected blocks command operation program command on a protected block no progr amming operation is performed, and the flash memory automatically returns to read mode. block erase command on a protected block no eras e operation is performed, and the flash memory automatically returns to read mode. chip erase command when all the blocks are protected no erase operation is performed, and the flash memory automatically returns to read mode. chip erase command when any blocks are protected only t he unprotected blocks are erased. upon completion, the flash memory automatically returns to read mode. multi-block erase command when any blocks are protected only the unprotected blocks are erased. upon completion, the flash memory automatically returns to read mode. any commands written during the block protect algor ithm are ignored. a hardware reset immediately terminates the block protect operation. the block protect command that was interrupted should be re-initiated once the flash memory is ready to accept another command sequence. 3.6.12 block unprotect operation block unprotect operation is performed for indivi dual area (flash 0 and flash 1). set a[19] in accordance to the area required for bl ock unprotect by the bus cycle. af ter completion of the seventh bus write cycle, fcls is 0 during block unprotect operation, and 1 after block unprotect operation. any commands written during the block unprotect algorithm are ignored. the hardware reset immediately terminates the bloc k unprotect operation. the block pr otect command should be reinitiated once the flash memory is ready to accept another command sequence. use the verify block protect command to verify the protect status of a block. 3.6.13 verify block protect command the verify block protect command is used to verify the protect status of a block. verify block protect is a four-bus-cycle operation. the address of the block to be verified is given in the fourth cycle. any address within the block range will suffice, provided a0 = a1 = a2 = a3 = 0, a4 = 1 and a6 = 0. to get correct data, a 32-bit read must be performed. use the last read as valid data. if the selected block is protected, a value of 0x0000_0001 is returned. if the selected block is not protected, a value of 0x0000_0000 is returned. following the f ourth bus cycle, an additiona l block address may be read. the verify block protect command does not return the flash memory to read mode. either the read/reset command or a hardware reset is required to reset the flash memory to read mode or to write the next command.
TMP1962F10AXBG tmp1962f-60 3.6.14 write operation status as shown in table 3.19, the flash memory provides several flag bits to determine the status of an embedded operation: dq7, dq5 and dq3. these status bits can be read during an embedded operation using the same timing as for read mode. the flash me mory automatically returns to read mode when an embedded operation completes. the status of an embedded program operation can be monitored to determine whether the hardware sequence flag duri ng an embedded operation, or the data read after completion of an embedded operation match the cell data. read of the hardware sequence flag is performed by checking start of embedded operation (flcs=0). during the embedded program operation, the system must provide the program address (with a0 = 0 and a1 = 0) to read valid status information. during the embedded erase operation, the system must provide an address (with a0 = 0 and a1 = 0) within an y of the blocks selected for erasure to read valid status information. ? dq7 (data polling) the data polling bit, dq7, indicates to the host system the status of the embedded operation. data polling is valid after the final bus write cycle of an embedded command sequence. when the embedded program algorithm is in progress, an attempt to read the flash memory will produce the complement of the data last wr itten to dq7. upon completion of the embedded program algorithm, an attempt to read the flash memory will produce the true data last written to dq7. therefore, the system can use dq7 to determine whether the embedded program algorithm is in progress or complete. when the embedded erase algorithm is in progress, an attempt to read the flash memory will produce a 0 at the dq7 output. upon completion of the embedded erase algorithm, the flash memory will produce a 1 at the dq7 output. if there is a failure during an embedded operation, dq7 continues to output the same value. thus, dq7 must always be polled in conjunction with the exceeded timing limits (dq5) flag. figure 3.21 shows the dq7 polling algorithm. the flash memory disables address latching wh en an embedded operation is complete. data polling must be performed with a valid programmed address or an address within any of the non-protected blocks selected for erasure. ? dq5 (exceeded timing limits) dq5 produces a 0 while the program or erase operation is in progress normally. dq5 produces a 1 to indicate that the program or erase time has exceeded the specifi ed internal limit. this is a failure condition that indicates the program or erase cycle was not successfully completed. the dq5 failure condition also appears if the system tries to program a 1 to a location that was previously programmed to a 0. only an erase opera tion can change a 1 back to a0. in this case, the embedded program algorithm halts the ope ration. once the operation has exceeded the timing limits, dq5 will indicate a 1. note that this is not a device failure condition since the flash memory was used incorrectly. under both these conditions, the flash memory remains locked in embedded operation mode. the system must issue the read/reset command to return the flash memory to read mode.
TMP1962F10AXBG tmp1962f-61 ? dq3 (block erase timer) after the completion of the sixth bus cycle of the auto block erase command sequence, the block erase time-out window of 50 m begins. the erase operation will begin after the time-out has expired. when the time-out is complete and the erase operation has begun, dq3 switches from 0 to 1. if dq3 is 0, the flash memory will accept additional auto block erase commands. each time an auto block erase command is written, the time-out window is reset. to ensure that the command has been accepted, the system shoul d check dq3 prior to and following each auto block erase command. if dq3 is 1 on the second status check, the command might not have been accepted. 3.6.15 flash control/status register this is an 8-bit register that indicates the ready/busy status of an embedded algorithm and controls the security feature. 7 6 5 4 3 2 1 0 flcs bit symbol flrmsk rdy/bsy (0xffff_e520) read/write w r reset value 0 1 0 function flash reset mask enable 1: reset a flash control circuitry 0: unreset a flash control circuitry ready/ busy 0: embedded algorithm is in progress. 1: embedded algorithm is complete. must be written as ?0?. figure 3.18 flash control/status register ? bit 2: ready/busy flag bit( in programmer mode, the ale pin functions as the rdy/ bsy pin. the host system can monitor the state of this pin to determine whether an embedded algorithm is in progress or complete. the cpu can poll the rdy/bsy bit in the flcs register for the same purpose. the rdy/bsy bit is cleared to 0 when the flash me mory is actively erasing or programming. the rdy/bsy bit is set to 1 when an embedded operation has completed and the flash memory is ready to accept the next command. if any failure occurs during the program or erase operation, this bit remains cleared. a hardware reset sets this bit. the rdy/bsy bit is cleared upon completion of the final bus write cycle of an embedded operation command, with one exception. in the case of the auto block erase command, this bit is cleared after the time-out has expired. any command is ignored while the rdy/bsy bit is cleared.
TMP1962F10AXBG tmp1962f-62 ? bit 7: flash reset mask bit an interval of 30 s (t.b.d.) is allowed to elapse before starting the processor core operation after a reset upon power on, which is required to initialize an on-chip flas h control circuitry. sysrdy is signaled to indicate the start of the processor core operation from outside of tmp1962. after the processor core is reset, sysrdy switches from low to high. the reset operation after power on (do not power off) is controlled by bit 7 (flrmsk) of the flash control/status register (flcs) in the flash control part. when the flrmsk bit is 0 (initial value), the flash control circuitry is always initialized. when the flrmsk bit is set to 1, the flash control circuitry is not initialized. (read of the on-chip flash memory is performed correctly.) in this case, the interval of 30 s (t.b.d.) is not required for the fl ash control circuitry to be stable after a reset. immediately the processor core starts operation, and the sysrdy signal switches to high. the value set to the flrmsk bit is retained until power off. set flrmsk=1 commonly by initial setting afterreset. 3.6.16 flash security the TMP1962F10AXBG flash memory supports not only on-board programming but also programming using a general-purpose programmer. therefore, the TMP1962F10AXBG flash memory provides a security feature to pr event intrusive access to the flash memory while in programmer mode. the TMP1962F10AXBG is secured by all eight blocks being protected, and the contents of a flash memory can not be read by a programmer. ? securing the flash (disabling read accesses) securing the flash memory disables a general-purpose programmer to read its contents. to turn on the security feature, once programming is comple te, protect all eight blocks. that secures the flash memory. if one of eight blocks is unprotected, the flash memory is unsecured. in on-board operating modes, the cpu can read th e flash memory even if the security is on. when the security is on, any reads by programming equipment will always return a word-length value of 0x0098. ? unsecuring the flash (enabling read accesses) the security feature is designed to disable reads of the flash memory by programming equipment. while the TMP1962F10AXBG is soldered on a board, the cpu can always read the flashmemory, regardless of whether or not the s ecurity is on. since the flash memory is placed under control of a user?s application program in on-board operating modes, it is not easy for third parties to perform intrusiv e access to the flash memory. theref ore, within the confines of a board, the flash memory does not need to be secured. to turn off the security feature, unprotect eight blocks. unsecuring the flash memory enab les the flash memory erase operation to occur before turning off the security feature. after a flash memory has been erased, the flash memory unsecure operation is completed by erasing the block protect bit. note: the flash control/status register must be accessed as a 32-bit quantity.
TMP1962F10AXBG tmp1962f-63 3.6.17 command definition table 3.16 on-board programming mode command definition bus c y cles 1st cycle (write) 2nd cycle (write) 3rd cycle (write) 4th cycle (read/write) 5th cycle (read/write) command sequence cycles required addr data addr data addr data addr data addr data read/reset 1 0xxxxx f0h read/reset 3 0x5554 aah 0xaaa8 55h 0x5554 f0h ra rd auto program 4 0x5554 aah 0xaaa8 55h 0x5554 a0h pa pd auto chip erase 6 0x5554 aah 0xaaa8 55h 0x5554 80h 0x5554 aah 0xaaa8 55h auto block erase 6 0x5554 aah 0xaaa8 55h 0x5554 80h 0x5554 aah 0xaaa8 55h block protect 7 0x5554 aah 0xaaa8 55h 0x5554 9ah 0x5554 aah 0xaaa8 55h block unprotect 7 0x5554 aah 0xaaa8 55h 0x5554 6ah 0x5554 aah 0xaaa8 55h id read/block protect verify 4 0x5554 aah 0xaaa8 55h 0x5554 90h ia/bpa id/bd ( continued from above) bus cycles 6th cycle (write) 7th cycle (write) command sequence cycles required addr data addr data read/reset 1 read/reset 3 auto program 4 auto chip erase 6 0x5554 10h auto block erase 6 ba 30h block protect 7 0x5554 9ah bpa 9ah block unprotect 7 0x5554 6ah 0x5554 6ah auto security on (note 1) 4 note 1: after every bus write cycle, execute sync and nop in sequence. note 2: set the value corresponding the flash memory a ddress to 16-bit through 19-bit in every bus write cycle.
TMP1962F10AXBG tmp1962f-64 the addresses to be provided by the cpu are shown below. table 3.17 addresses provided by the cpu cpu addresses: a23?a0 command address a23?a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0xxxx0 x x x x x x x x x x x x 0 0 0 0 0x0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0xaaa8 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0x5554 flash memory block 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 ? f0h, aah, 55h, a0h, 80h, 10h, 30h: command data. write command data as a byte quantity. ? ra: read address rd: read data ? pa: program address pd: program data the address must be a multiple of four. write data on a word-by-word basis. ? ba: block address (ba0?ba6) refer to table 3.18. ? bpa: verify block protect address bd: block protect data refer to table 3.18. the address of the block to be verified can be any of the addresses within the block, with a6 = 0, a4 = 1, a3 = 0, a1 = 0 and a0 = 0. if a block is protected, a value of 0x0000_0001 will be returned. if a block is not protected, a valu e of 0x0000_0000 will be returned. ? ia: id read address ? id: id data
TMP1962F10AXBG tmp1962f-65 table 3.18 block erase addresses user boot mode boot mode a19 a18 a17 block-0 0x1fc0_0000 - 0x1fc1_ffff ( or 0x4000 _ 0000 - 0x4001 _ ffff ) 0x1fc0_0000 - 0x1fc1_ffff 128 kbyte 0 0 0 block-1 0x1fc2_0000 - 0x1fc3_ffff (or 0x4002_0000 - 0x4003_ffff) 0x1fc2_0000 - 0x1fc3_ffff 128 kbyte 0 0 1 block-2 0x1fc4_0000 - 0x1fc5_ffff (or 0x4004_0000 - 0x4005_ffff) 0x1fc4_0000 - 0x1fc5_ffff 128 kbyte 0 1 0 flash0 block-3 0x1fc6_0000 - 0x1fc7_ffff (or 0x4006_0000 - 0x4007_ffff) 0x1fc6_0000 - 0x1fc7_ffff 128 kbyte 0 1 1 block-4 0x1fc8_0000 - 0x1fc9_ffff (or 0x4008_0000 - 0x4009_ffff) 0x1fc8_0000 - 0x1fc9_ffff 128 kbyte 1 0 0 block-5 0x1fca_0000 - 0x1fcb_ffff (or 0x400a_0000 - 0x400b_ffff) 0x1fca_0000 - 0x1fcb_ffff 128 kbyte 1 0 1 block-6 0x1fcc_0000 - 0x1fcd_ffff (or 0x400c_0000 - 0x400d_ffff) 0x1fcc_0000 - 0x1fcd_ffff 128 kbyte 1 1 0 flash1 block-7 0x1fce_0000 - 0x1fcf_ffff (or 0x400e_0000 - 0x400e_ffff) 0x1fce_0000 - 0x1fcf_ffff 128 kbyte 1 1 1 the address of the block to be erased can be any of the addresses within that block with a0=0 and a1=0. example: to select ba0 in user boot mode, provide any address in the range between 0x1fc0_0000 and 0x1fc1_ffff. table 3.19 write status flags status d7 (dq7) d5 (dq5) d3 (dq3) auto program 7 dq 0 0 auto erase (during the time-out window) 0 0 0 embedded operation in progress auto erase 0 0 1 auto program 7 dq 1 1 time-out in embedded operation auto erase 0 1 1 note: d31?d8, d6, d4 and d2?d0 are don?t-cares.
TMP1962F10AXBG tmp1962f-66 3.6.18 embedded algorithms figure 3.19 auto program operation auto program command sequence (shown below) last address? start no data polling bit (read as a word quantity) ye s auto program done address = address + 4 (word-by-word) auto program command sequence (address/data) 0x5554 / 0xaa 0xaaa8 / 0x55 0x5554 / 0xa0 program address (a1 = a0 = 0) / program data (word-by-word)
TMP1962F10AXBG tmp1962f-67 figure 3.20 auto erase operations auto erase command sequence (shown below) start data polling bit (read as a word quantity) auto erase done auto chip erase command sequence (address/data) 0x5554 / 0xaa 0xaaa8 / 0x55 0x5554 / 0x80 0x5554 / 0xaa 0xaaa8 / 0x55 0x5554 / 0x10 auto block/multi-block erase command sequence (address/data) 0x5554 / 0xaa 0xaaa8 / 0x55 0x5554 / 0x80 0x5554 / 0xaa 0xaaa8 / 0x55 block address / 0x30 block address / 0x30 a dditional addresses for auto multi-block erase (each within 50 s) block address / 0x30
TMP1962F10AXBG tmp1962f-68 figure 3.21 data polling (dq7) algorithm read a word. addr = va dq5 = 1 ? start y es dq7 = data ? read a word addr = va no dq7 = data ? fail pass y es y es no no (va: valid address) read a word. addr. = va compare with 32-bit quantity.
TMP1962F10AXBG 2006-02-21 tmp1962f-69 4. electrical characteristics the letter x in equations presented in this chapter re presents the cycle period of the fsys clock selected through the programming of the syscr1.sysck bit. the fsys clock may be derived from either the high-speed or low-speed crystal oscillator. the programming of the clock gear function also affects the fsys frequency. all relevant values in this chapter are calculated with the high-speed (fc) system clock (syscr1.sysck = 0) and a clock gear factor of 1/fc (syscr1.gear[1:0] = 00). 4.1 absolute maximum ratings parameter symbol rating unit v cc2 (core) ? 0.3 to 3.6 v cc3 (i/o) ? 0.3 to 4.0 avcc (a/d) ? 0.3 to 3.6 supply voltage fvcc3 (l1 pin) ? 0.3 to 4.0 v input voltage v in ? 0.3 to v cc + 0.3 v per pin i ol 5 low-level output current total i ol 50 per pin i oh ? 5 high-level output current total i oh 50 ma power dissipation (ta = 85c) pd 600 mw soldering temperature (10 s) t solder 260 c storage temperature t stg ? 65 to 150 c except during flash w/e ? 20 to 85 operating temperature during flash w/e t opr 10 to 60 c write/erase cycles n ew 100 cycle v cc 2 = dvcc21 = dvcc22 = fvcc2 = cvcc2, v cc 3 = dvcc3n (n = 1 to 4), avcc = avcc31 = avcc32, v ss = dvss = fvss = avss = cvss note: absolute maximum ratings are limiting valu es of operating and environmental conditions which should not be exceeded under the worst possible c onditions. the equipment manufacturer should design so that no absolute maximum ratings valu e is exceeded with respect to current, voltage, power dissipation, temperature, etc. exposure to conditions beyond those listed above may cause permanent damage to the device or affect dev ice reliability, which could increase potential risks of personal injury due to ic blowup and/or burning.
TMP1962F10AXBG 2006-02-21 tmp1962f-70 4.2 dc electrical characteristics (1/4) ta = ?20 to 85c parameter symbol conditions min typ (note 1) max unit dvcc2m (m = 1 to 2) fosc = 10 to 13.5 mhz fsys = 3.75 to 40.5 mhz pllon, intlv = ?h? 2.2 2.7 dvcc3n (n = 1 to 4) fsys = 3.75 to 40.5 mhz 1.65 3.3 supply voltage fvcc2 = cvcc2 = dvcc21 = dvcc22 fvss = cvss = dvss = 0 v fvcc3 fsys = 3.75 to 40.5 mhz 2.9 3.6 v 2.7 v avcc32 avcc31 3.5 v p7-p9 (used as a port) v il1 1.65 avcc32 < 2.7 v 0.3 avcc31 0.3 avcc32 1.65 v dvcc3n 3.3 v (n = 1 to 4) p0-p6, pa-pc, pd0-pd6, pe0-pe2, pf2-pf7, pg-ph, pi7, pj1-pj4, pl-pp v il2 2.2 v dvcc2m 2.7 v (m = 1 to 2) 0.3 dvcc3n 0.2 dvcc2m 2.7 v dvcc3n 3.3 v (n = 1 to 4) 0.15 dvcc3n pd7, pe3-pe7, pf0-pf1, pi0-pi6, pj0, pk, plloff , rstpup, reset dreset , dbge sdi/ dint , tck, tms, tdi, trst nmi , bw0, bw1 v il3 1.65 v dvcc3n < 2.7 v (n = 1 to 4) 2.2 v dvcc2m 2.7 v (m = 1 to 2) 0.1 dvcc3n 0.1 dvcc2m low-level input voltage x1 v il4 2.2 v cvcc2 2.7 v ? 0.3 0.1 cvcc2 v note 1: ta = 25c, dvcc3n = 3.0 v, dvcc2m = 2.5 v, avcc3 = 3.3 v, unless otherwise noted.
TMP1962F10AXBG 2006-02-21 tmp1962f-71 4.3 dc electrical characteristics (2/4) ta = ?20 to 85c parameter symbol conditions min typ. (note 1) max unit 2.7 v avcc32 avcc31 3.5 v p7-p9 (used as a port) v ih1 1.65 avcc32 < 2.7 v 0.7 avcc31 0.7 avcc32 1.65 v dvcc3n 3.3 v (n = 1 to 4) 0.7 dvcc3n p0-p6, pa-pc, pd0-pd6, pe0-pe2, pf2-pf7, pg-ph, pi7, pj1-pj4, pl-pp v ih2 2.2 v dvcc2m 2.7 v (m = 1 to 2) 0.8 dvcc2m 2.7 v dvcc3n 3.3 v (n = 1 to 4) 0.85 dvcc3n pd7, pe3-pe7, pf0-pf1, pi0-pi6, pj0, pk, plloff , rstpup, reset dreset , dbge sdi/ dint , tck, tms, tdi, trst nmi , bw0, bw1 v ih3 1.65 v dvcc3n < 2.7 v (n = 1 to 4) 2.2 v dvcc2m 2.7 v (m = 1 to 2) 0.9 dvcc3n 0.9 dvcc2m dvcc2m + 0.3 dvcc3n + 0.3 high-level input voltage x1 v ih4 2.2 v cvcc2 2.7 v 0.9 cvcc2 v i ol = 2 ma dvcc3n 2.7 v 0.4 low-level output voltage v ol i ol = 500 a dvcc3n < 2.7 v dvcc2m 2.7 v 0.2 dvcc3n 0.4 0.2 dvcc2 0.4 i oh = ? 2 ma dvcc3n 2.7 v 2.4 high-level output voltage v oh i oh = ? 500 a dvcc3n < 2.7 v dvcc2m 2.7 v 0.8 dvcc3n 0.8 dvcc2 v note 1: ta = 25c, dvcc3n = 3.0 v, dvcc2m = 2.5 v, avcc3 = 3.3 v, unless otherwise noted.
TMP1962F10AXBG 2006-02-21 tmp1962f-72 4.4 dc electrical characteristics (3/4) ta = ?20 to 85c parameter symbol conditions min typ. (note 1) max unit input leakage current i li 0.0 v in dvcc2m (m = 1 to 2) 0.0 v in dvcc3n (n = 1 to 4) 0.0 v in avcc31 0.0 v in avcc32 0.02 5 output leakage current i lo 0.2 v in dvcc2m ? 0.2 (m = 1 to 2) 0.2 v in dvcc3n ? 0.2 (n = 1 to 4) 0.2 v in avcc31 ? 0.2 0.2 v in avcc32 ? 0.2 0.05 10 a power-down voltage (stop mode ram backup) v stop (dvcc2) v il2 = 0.2dvcc2m, v il3 = 0.1dvcc2m v ih2 = 0.8dvcc2m, v ih3 = 0.9dvcc2m 2.2 2.7 v pull-up resister at reset rrst 2.2 v dvcc21 2.7 v 20 50 240 k ? 2.7 v dvcc3n 3.3 v (n = 2, 4) 0.4 0.9 schmitt w idth pd7, pe3-pe7, pf0-pf1, pi0-pi6, pj0, pk, plloff , rstpup, reset , dreset , dbge , sdi/ dint , tck, tms, tdi, trst , nmi , bw0, bw1 vth 1.65 v dvcc3n < 2.7 v (n = 2, 4) 2.2 v dvcc2m 2.7 v (m = 1 to 2) 0.3 0.6 v dvcc3n = 3.0 v 0.3 v (n = 2 to 4) 15 50 100 dvcc3n = 2.5 v 0.2 v (n = 2 to 4) 20 50 240 programmable pull-up/ pull-down resistor p32-p37,p40-p43 key0-keyd, dreset, dbge , sdi/ dint , tck, tms, tdi, trst pkh dvcc3n = 2.0 v 0.2 v (n = 2 to 4) 25 160 600 k ? pin capacitance (except power supply pins) c io fc = 1 mhz 10 pf note 1: ta = 25c, dvcc3n = 3.0 v, dvcc2m = 2.5 v, avcc3 = 3.3 v, unless otherwise noted.
TMP1962F10AXBG 2006-02-21 tmp1962f-73 4.5 dc electrical characteristics (4/4) dvcc2m = fvcc2 = cvcc2 = 2.5 v 0.2 v, fvcc3 = 3.3 v 0.3 v, dvcc3n = 3.0 v 0.3 v, avcc3m = 3.3 v 0.2 v ta = -20 to 85c (n = 1 to 4, m = 1, 2) parameter symbol conditions min typ. (note 1) max unit normal (note 2): gear = 1/1 90 110 idle (doze) 40 60 idle (halt) f sys = 40.5 mhz (f osc = 13.5 mhz, pllon) intlv = ?h? 33 50 ma stop i cc dvcc2m = fvcc2 = cvcc2 = 2.2 to 2.7 v dvcc3n = 1.65 to 3.3 v avcc3m = 2.7 to 3.5 v fvcc3 = 3.0 to 3.6 v 55 900 a note 1: ta = 25c, dvcc2m = 2.5 v, dvcc3n = 3. 0 v, avcc3m = 3.3 v, unless otherwise noted. note 2: measured with the cpu dhr ystone operating, all i/o peripheral s channel on, and 16-bit external bus operated with 4 system clocks. note 3: the supply current flowing through the dvcc2m, fvcc2, dvcc 3n, cvcc2, fvcc3 and avcc3m pins is included in the digital supply current parameter (icc).
TMP1962F10AXBG 2006-02-21 tmp1962f-74 4.6 adc electrical characteristics dvcc15=cvcc15=1.5v ? 0.15v,dvcc2 1 2.5v ? 0.2v, dvcc3n 1 3.0v ? 0.3v , avcc3m 1 3.0v ? 0.2v 5b1?? o1?zn1 parameter symbol condition min typ max unit 2.7 3.3 analog reference voltage (+) vrefh avccm 0.3 avcc avccm 0.3 analog reference voltage (?) vrefl avss avss avss 0.2 analog input voltage vain vrefl vrefh v during conversion admod1.vrefon 1 a vccm vrefh = 3.0v r 0.3v dvss = avss = vrefl 0.35 1.0 ma analog supply current not conversion admod1.vrefon 0 iref a vccm = vrefh = 3.0v r 0.3v dvss = avss = vrefl 0.02 10 p a analog input capacitance 5.0 pf analog input impedance 5.0 :
integral linearity error r 2 r 3 lsb differential linearity error r 1.5 r 3 lsb off set error r 2 r 3 lsb gain error a vccm vrefh = 3.0v r 0.2v dvss = avss = vrefl a in input impedance r ? 13.3k
c ? 20pf a vccm capacito r ? 10 f vrefh capacito r ? 10 f conversion time ? 7.9 s note* r 2 r 6 lsb note 1: 1 lsb = (vrefh ? vrefl) / 1024 (v) note 2: the supply current flowing through the av cc pin is included in the digital supply current parameter (icc). "744 "*/ note*:recommend to connect an external capacitor* 0.1 f note 3: please shift to halt condition in ad converte r before changing the standby mode of this product to stop mode.
TMP1962F10AXBG 2006-02-21 tmp1962f-75 4.7 ac electrical characteristics 4.7.1 multiplex bus mode (1) dvcc2m = fvcc2 = cvcc2 = 2.5 v 0.2 v, fvcc3 = 3.3 v 0.3 v, avcc3m = 3.3 0.2 v, dvcc33 = 3.0 v 0.3 v, ta = -20 to 85 c (m = 1 to 2) 1. ale width = 0.5 clock cycl e, 1 programmed wait state equation 40.5 mhz (fsys) (note) no. parameter symbol min max min max unit 1 system clock period (x) t sys 24.6 ns 2 a0-a15 valid to ale low t al 0.5x ? 4.3 8 ns 3 a0-a15 hold after ale low t la 0.5x ? 1.8 10.5 ns 4 ale pulse width high t ll 0.5x ? 0.3 12 ns 5 ale low to rd , wr or hwr asserted t lc 0.5x ? 2.3 10 ns 6 rd , wr or hwr negated to ale high t cl x ? 0.6 24 ns 7 a0-a15 valid to rd , wr or hwr asserted t acl x ? 5.1 19.5 ns 8 a16-a23 valid to rd , wr or hwr asserted t ach x ? 5.1 19.5 ns 9 a16-a23 hold after rd , wr or hwr negated t car x ? 1.6 23 ns 10 a0-a15 valid to d0-d15 data in t adl x (2 + w) ? 35.8 38 ns 11 a16-a23 valid to d0-d15 data in t adh x (2 + w) ? 35.8 38 ns 12 rd asserted to d0-d15 data in t rd x (1 + w) ? 30.7 18.5 ns 13 rd width low t rr x (1 + w) ? 2.7 46.5 ns 14 d0-d15 hold after rd negated t hr 0 0 ns 15 rd negated to next a0-a15 output t rae x ? 0.1 24.5 ns 16 wr or hwr width low t ww x (1 + w) ? 3.2 46 ns 17 d0-d15 valid to wr or hwr negated t dw x (1 + w) ? 4.2 45 ns 18 d0-d15 hold after wr or hwr negated t wd x ? 0.1 24.5 ns 19 a16-a23 valid to wait input t awh x (3 + 0.5) ? 21.6 64.5 ns 20 a0-a15 valid to wait input t awl x (3 + 0.5) ? 21.6 64.5 ns 21 wait hold after rd , wr or hwr asserted t cw x (0.5 + 3 + n ? 2) ? 4.1 x (1.5 + 3 + n ? 2) ? 18.7 57.4 67.4 ns note: no. 1 to 18 indicate the values obtained with 1 programmed wait state. n0. 19 and 20 indicate the values obtained with 4 externally generated wait states with n = 1. ac measurement conditions: ? output levels: high = 0.8dvcc33 v/low 0.2dvcc33 v, cl = 30 pf ? input levels: high = 0.7dvcc33 v/low 0.3dvcc33 v w: number of wait state cycles inserted (0 to 7 for programmed wait insertion) n: value of n for (3 + n) wait insertion
TMP1962F10AXBG 2006-02-21 tmp1962f-76 2. ale width = 1.5 clock cycl es, 1 programmed wait state equation 40.5 mhz (fsys) (note) no. parameter symbol min max min max unit 1 system clock period (x) t sys 24.6 ns 2 a0-a15 valid to ale low t al 1.5x ? 3.9 33 ns 3 a0-a15 hold after ale low t la 0.5x ? 1.8 10.5 ns 4 ale pulse width high t ll 1.5x ? 0.4 36.5 ns 5 ale low to rd , wr or hwr asserted t lc 0.5x ? 2.4 10 ns 6 rd , wr or hwr negated to ale high t cl x ? 0.6 24 ns 7 a0-a15 valid to rd , wr or hwr asserted t acl 2x ? 5.2 44 ns 8 a16-a23 valid to rd , wr or hwr asserted t ach 2x ? 5.2 44 ns 9 a16-a23 hold after rd , wr or hwr negated t car x ? 1.6 23 ns 10 a0-a15 valid to d0-d15 data in t adl x (3 + w) ? 35.9 62.5 ns 11 a16-a23 valid to d0-d15 data in t adh x (3 + w) ? 35.9 62.5 ns 12 rd asserted to d0-d15 data in t rd x (1 + w) ? 30.7 18.5 ns 13 rd width low t rr x (1 + w) ? 2.7 46.5 ns 14 d0-d15 hold after rd negated t hr 0 0 ns 15 rd negated to next a0-a15 output t rae x 24.6 ns 16 wr or hwr width low t ww x (1 + w) ? 3.2 46 ns 17 d0-d15 valid to wr or hwr negated t dw x (1 + w) ? 4.2 45 ns 18 d0-d15 hold after wr or hwr negated t wd x ? 0.1 24.5 ns 19 a16-a23 valid to wait input t awh x (4 + 0.5) ? 21.7 89 ns 20 a0-a15 valid to wait input t awl x (4 + 0.5) ? 21.7 89 ns 21 wait hold after rd , wr or hwr asserted t cw x (0.5 + 3 + n ? 2) ? 4.1 x (1.5 + 3 + n ? 2) ? 18.7 57.4 67.4 ns note: no. 1 to 18 indicate the values obtained with 1 programmed wait state. n0. 19 and 20 indicate the values obtained with 4 externally generated wait states with n = 1. ac measurement conditions: ? output levels: high = 0.8dvcc33 v/low 0.2dvcc33 v, cl = 30 pf ? input levels: high = 0.7dvcc33 v/low 0.3dvcc33 v w: number of wait state cycles inserted (0 to 7 for programmed wait insertion) n: value of n for (3 + n) wait insertion
TMP1962F10AXBG 2006-02-21 tmp1962f-77 (2) dvcc2m = fvcc2 = cvcc2 = 2.5 v 0.2 v, fvcc3 = 3.3 v 0.3 v, avcc3m = 3.3 0.2 v, dvcc33 = 2.5 v 0.2 v, ta = 20 to 85 c (m = 1 to 2) 1. ale width = 0.5 clock cycl e, 1 programmed wait state equation 40.5 mhz (fsys) (note) no. parameter symbol min max min max unit 1 system clock period (x) t sys 24.6 ns 2 a0-a15 valid to ale low t al 0.5x ? 2.3 10 ns 3 a0-a15 hold after ale low t la 0.5x ? 1.8 10.5 ns 4 ale pulse width high t ll 0.5x ? 0.3 12 ns 5 ale low to rd , wr or hwr asserted t lc 0.5x ? 2.3 10 ns 6 rd , wr or hwr negated to ale high t cl x ? 0.6 24 ns 7 a0-a15 valid to rd , wr or hwr asserted t acl x ? 5.1 19.5 ns 8 a16-a23 valid to rd , wr or hwr asserted t ach x ? 5.1 19.5 ns 9 a16-a23 hold after rd , wr or hwr negated t car x ? 1.6 23 ns 10 a0-a15 valid to d0-d15 data in t adl x (2 + w) ? 36.8 37 ns 11 a16-a23 valid to d0-d15 data in t adh x (2 + w) ? 36.8 37 ns 12 rd asserted to d0-d15 data in t rd x (1 + w) ? 31.7 17.5 ns 13 rd width low t rr x (1 + w) ? 2.2 47 ns 14 d0-d15 hold after rd negated t hr 0 0 ns 15 rd negated to next a0-a15 output t rae x ? 0.1 24.5 ns 16 wr or hwr width low t ww x (1 + w) ? 2.7 46.5 ns 17 d0-d15 valid to wr or hwr negated t dw x (1 + w) ? 3.8 45.5 ns 18 d0-d15 hold after wr or hwr negated t wd x ?0.1 24.5 ns 19 a16-a23 valid to wait input t awh x (3 + 0.5) ? 22.6 63.5 ns 20 a0-a15 valid to wait input t awl x (3 + 0.5) ? 22.6 63.5 ns 21 wait hold after rd , wr or hwr asserted t cw x (0.5 + 3 + n ? 2) ? 5.1 x (1.5 + 3 + n ? 2) ? 19.7 56.4 66.4 ns note: no. 1 to 18 indicate the values obtained with 1 programmed wait state. n0. 19 and 20 indicate the values obtained with 4 externally generated wait states with n = 1. ac measurement conditions: ? output levels: high = 0.8dvcc33 v/low 0.2dvcc33 v, cl = 30 pf ? input levels: high = 0.7dvcc33 v/low 0.3dvcc33 v w: number of wait state cycles inserted (0 to 7 for programmed wait insertion) n: value of n for (3 + n) wait insertion
TMP1962F10AXBG 2006-02-21 tmp1962f-78 2. ale width = 1.5 clock cycl es, 1 programmed wait state equation 40.5 mhz (fsys) (note) no. parameter symbol min max min max unit 1 system clock period (x) t sys 24.6 ns 2 a0-a15 valid to ale low t al 1.5x ? 2.4 34.5 ns 3 a0-a15 hold after ale low t la 0.5x ? 1.8 10.5 ns 4 ale pulse width high t ll 1.5x ? 0.4 36.5 ns 5 ale low to rd , wr or hwr asserted t lc 0.5x ? 2.4 10 ns 6 rd , wr or hwr negated to ale high t cl x ? 0.6 24 ns 7 a0-a15 valid to rd , wr or hwr asserted t acl 2x ? 5.2 44 ns 8 a16-a23 valid to rd , wr or hwr asserted t ach 2x ? 5.2 44 ns 9 a16-a23 hold after rd , wr or hwr negated t car x ? 1.6 23 ns 10 a0-a15 valid to d0-d15 data in t adl x (3 + w) ? 36.9 61.5 ns 11 a16-a23 valid to d0-d15 data in t adh x (3 + w) ? 36.9 61.5 ns 12 rd asserted to d0-d15 data in t rd x (1 + w) ? 31.7 17.5 ns 13 rd width low t rr x (1 + w) ? 2.2 47 ns 14 d0-d15 hold after rd negated t hr 0 0 ns 15 rd negated to next a0-a15 output t rae x ? 0.1 24.5 ns 16 wr or hwr width low t ww x (1 + w) ? 2.7 46.5 ns 17 d0-d15 valid to wr or hwr negated t dw x (1 + w) ? 3.8 45.5 ns 18 d0-d15 hold after wr or hwr negated t wd x ?0.1 24.5 ns 19 a16-a23 valid to wait input t awh x (4 + 0.5) ? 22.6 88.1 ns 20 a0-a15 valid to wait input t awl x (4 + 0.5) ? 22.6 88.1 ns 21 wait hold after rd , wr or hwr asserted t cw x (0.5 + 3 + n ? 2) ? 5.1 x (1.5 + 3 + n ? 2) ? 19.7 56.4 66.4 ns note: no. 1 to 18 indicate the values obtained with 1 programmed wait state. n0. 19 and 20 indicate the values obtained with 4 externally generated wait states with n = 1. ac measurement conditions: ? output levels: high = 0.8dvcc33 v/low 0.2dvcc33 v, cl = 30 pf ? input levels: high = 0.7dvcc33 v/low 0.3dvcc33 v w: number of wait state cycles inserted (0 to 7 for programmed wait insertion) n: value of n for (3 + n) wait insertion
TMP1962F10AXBG 2006-02-21 tmp1962f-79 (3) dvcc2m = fvcc2 = cvcc2 = 2.5 v 0.2 v, fvcc3 = 3.3 v 0.3 v, avcc3m = 3.3 0.2 v, dvcc33 = 1.8 v 0.15 v, ta = 20 to 85 c (m = 1 to 2) 1. ale width = 0.5 clock cycl e, 2 programmed wait state equation 40.5 mhz (fsys) (note) no. parameter symbol min max min max unit 1 system clock period (x) t sys 24.6 33333 ns 2 a0-a15 valid to ale low t al 0.5x ? 2.3 10 ns 3 a0-a15 hold after ale low t la 0.5x ? 1.8 10.5 ns 4 ale pulse width high t ll 0.5x ? 0.3 12 ns 5 ale low to rd , wr or hwr asserted t lc 0.5x ? 2.3 10 ns 6 rd , wr or hwr negated to ale high t cl x ? 0.6 24 ns 7 a0-a15 valid to rd , wr or hwr asserted t acl x ? 5.1 19.5 ns 8 a16-a23 valid to rd , wr or hwr asserted t ach x ? 5.1 19.5 ns 9 a16-a23 hold after rd , wr or hwr negated t car x ? 1.6 23 ns 10 a0-a15 valid to d0-d15 data in t adl x (2 + w) ? 42.4 56 ns 11 a16-a23 valid to d0-d15 data in t adh x (2 + w) ? 42.4 56 ns 12 rd asserted to d0-d15 data in t rd x (1 + w) ? 37.3 36.5 ns 13 rd width low t rr x (1 + w) ? 2.3 71.5 ns 14 d0-d15 hold after rd negated t hr 0 0 ns 15 rd negated to next a0-a15 output t rae x ? 0.1 24.5 ns 16 wr or hwr width low t ww x (1 + w) ? 2.8 71 ns 17 d0-d15 valid to wr or hwr negated t dw x (1 + w) ? 3.8 70 ns 18 d0-d15 hold after wr or hwr negated t wd x ? 0.1 24.5 ns 19 a16-a23 valid to wait input t awh x (3 + 0.5) ? 28.1 58 ns 20 a0-a15 valid to wait input t awl x (3 + 0.5) ? 28.1 58 ns 21 wait hold after rd , wr or hwr asserted t cw x (0.5 + 3 + n ? 2) ? 6.1 x (1.5 + 3 + n ? 2) ? 24.7 55.4 61.4 ns note: no. 1 to 18 indicate the values obtained with 1 programmed wait state. n0. 19 and 20 indicate the values obtained with 4 externally generated wait states with n = 1. ac measurement conditions: ? output levels: high = 0.8dvcc33 v/low 0.2dvcc33 v, cl = 30 pf ? input levels: high = 0.7dvcc33 v/low 0.3dvcc33 v w: number of wait state cycles inserted (0 to 7 for programmed wait insertion) n: value of n for (3 + n) wait insertion
TMP1962F10AXBG 2006-02-21 tmp1962f-80 2. ale width = 1.5 clock cycl es, 2 programmed wait states equation 40.5 mhz (fsys) (note) no. parameter symbol min max min max unit 1 system clock period (x) t sys 24.6 ns 2 a0-a15 valid to ale low t al 1.5x ? 2.4 34.5 ns 3 a0-a15 hold after ale low t la 0.5x ? 1.8 10.5 ns 4 ale pulse width high t ll 1.5x ? 0.4 36.5 ns 5 ale low to rd , wr or hwr asserted t lc 0.5x ? 2.3 10 ns 6 rd , wr or hwr negated to ale high t cl x ? 0.6 24 ns 7 a0-a15 valid to rd , wr or hwr asserted t acl 2x ? 5.2 44 ns 8 a16-a23 valid to rd , wr or hwr asserted t ach 2x ? 5.2 44 ns 9 a16-a23 hold after rd , wr or hwr negated t car x ? 1.6 23 ns 10 a0-a15 valid to d0-d15 data in t adl x (3 + w) ? 42.5 80.5 ns 11 a16-a23 valid to d0-d15 data in t adh x (3 + w) ? 42.5 80.5 ns 12 rd asserted to d0-d15 data in t rd x (1 + w) ? 37.3 36.5 ns 13 rd width low t rr x (1 + w) ? 2.3 71.5 ns 14 d0-d15 hold after rd negated t hr 0 0 ns 15 rd negated to next a0-a15 output t rae x ? 0.1 24.5 ns 16 wr or hwr width low t ww x (1 + w) ? 2.8 71 ns 17 d0-d15 valid to wr or hwr negated t dw x (1 + w) ? 3.8 70 ns 18 d0-d15 hold after wr or hwr negated t wd x ? 0.1 24.5 ns 19 a16-a23 valid to wait input t awh x (4 + 0.5) ? 28.1 82.6 ns 20 a0-a15 valid to wait input t awl x (4 + 0.5) ? 28.1 82.6 ns 21 wait hold after rd , wr or hwr asserted t cw x (0.5 + 3 + n ? 2) ? 6.1 x (1.5 + 3 + n ? 2) ? 24.7 55.4 61.4 ns note: no. 1 to 18 indicate the values obtained with 1 programmed wait state. n0. 19 and 20 indicate the values obtained with 4 externally generated wait states with n = 1. ac measurement conditions: ? output levels: high = 0.8dvcc33 v/low 0.2dvcc33 v, cl = 30 pf ? input levels: high = 0.7dvcc33 v/low 0.3dvcc33 v w: number of wait state cycles inserted (0 to 7 for programmed wait insertion) n: value of n for (3 + n) wait insertion
TMP1962F10AXBG 2006-02-21 tmp1962f-81 (1) read cycle timing, ale width = 0.5 clock cycle, 1 programmed wait state t car t rr t hr t adh t adl t la d0 to d15 t al t cl t ll a le internal clk a d0 to ad15 rd a0 to a15 t acl t ach t lc t rd a 16 to a23 bus cycle = 4 clk cycles s1 s2 s3 s1 w1 t rae 0 cs to 3 cs w / r
TMP1962F10AXBG 2006-02-21 tmp1962f-82 (2) read cycle timing, ale width = 1.5 clock cycles, 1 programmed wait state t car t rr t hr t adh t adl t la d0 to d15 t al t cl t ll ale internal clk ad0 to ad15 rd s0 s1 s2 s3 s0 a0 to a15 t acl t ach t lc t rd a16 to a23 w1 t rae 0 cs to 3 cs w / r bus cycle = 5 clk cycles
TMP1962F10AXBG 2006-02-21 tmp1962f-83 (3) read cycle timing, ale width = 1.5 clock cycles, 2 externally generated wait states with n = 1 t awl/h a le internal clk a d0 to a d15 rd a d16 to a d23 bus cycle = 6 clk cycles wait d0 to d15 s1 w s2 s3 s0 a0 to a15 w t cw 0 cs to 3 cs w / r
TMP1962F10AXBG 2006-02-21 tmp1962f-84 (4) read cycle timing, ale width = 1.5 clock cycles, 4 externally generated wait states with n = 1 t awl/h a le internal clk a d0 to a d15 rd a d16 to a d23 bus cycle = 8 clk cycles wait d0 to d15 s1 s2 s3 s0 a0 to a15 w t cw 0 cs to 3 cs w / r w w w
TMP1962F10AXBG 2006-02-21 tmp1962f-85 (5) write cycle timing, ale width = 1.5 clock cycles, zero wait state t ww t car t dw t la d0 to d15 t al t cl t ll a le internal clk a d0 to a d15 wr , hwr 0 cs to 3 cs w / r a0 to a15 t acl t ach t lc a d16 to a d23 bus cycle = 4 clk cycles t wd
TMP1962F10AXBG 2006-02-21 tmp1962f-86 4.7.2 separate bus mode (1) dvcc2m = fvcc2 = cvcc2 = 2.5 v 0.2 v, fvcc3 = 3.3 v 0.3 v, avcc3m = 3.3 0.2 v, dvcc33 = 3.0 v 0.3 v, ta = -20 to 85 c (m = 1 to 2) 1. syscr3 = 0, 1 programmed wait state equation 40.5 mhz (fsys) (note) no. parameter symbol min max min max unit 1 system clock period (x) t sys 24.6 ns 2 a0-a23 valid to rd , wr or hwr asserted t ac x ? 5.1 19.5 ns 3 a0-a23 hold after rd , wr or hwr negated t car x ? 1.6 23 ns 4 a0-a23 valid to d0-d15 data in t ad x (2 + w) ? 35.8 38 ns 5 rd asserted to d0-d15 data in t rd x (1 + w) ? 30.7 18.5 ns 6 rd width low t rr x (1 + w) ? 2.7 46.5 ns 7 d0-d15 hold after rd negated t hr 0 0 ns 8 rd negated to next a0-a23 output t rae x ? 0.1 24.5 ns 9 wr or hwr width low t ww x (1 + w) ? 3.2 46 ns 10 wr or hwr asserted to d0-d15 valid t do ? 1 ns 11 d0-d15 valid to wr or hwr negated t dw x (1 + w) ? 4.2 45 ns 12 d0-d15 hold after wr or hwr negated t wd x ? 0.1 24.5 ns 13 a0-a23 valid to wait input t aw x (3 + 0.5) ? 21.6 64.5 ns 14 wait hold after rd , wr or hwr asserted t cw x (0.5 + 3 + n ? 2) ? 4.1 x (1.5 + 3 + n ? 2) ? 18.7 57.4 67.4 ns note: no. 1 to 12 indicate the values obtained with 1 programmed wait state. n0. 13 and 14 indicate the values obtained with 4 externally generated wait states with n = 1. ac measurement conditions: ? output levels: high = 0.8dvcc33 v/low 0.2dvcc33 v, cl = 30 pf ? input levels: high = 0.7dvcc33 v/low 0.3dvcc33 v w: number of wait state cycles inserted (0 to 7 for programmed wait insertion) n: value of n for (3 + n) wait insertion
TMP1962F10AXBG 2006-02-21 tmp1962f-87 2. syscr3 = 1, 1 programmed wait state equation 40.5 mhz (fsys) (note) no. parameter symbol min max min max unit 1 system clock period (x) t sys 24.6 ns 2 a0-a23 valid to rd , wr or hwr asserted t ac 2x ? 5.2 44 ns 3 a0-a23 hold after rd , wr or hwr negated t car x ? 1.6 23 ns 4 a0-a23 valid to d0-d15 data in t ad x (3 + w) ? 35.9 62.5 ns 5 rd asserted to d0-d15 data in t rd x (1 + w) ? 30.7 18.5 ns 6 rd width low t rr x (1 + w) ? 2.7 46.5 ns 7 d0-d15 hold after rd negated t hr 0 0 ns 8 rd negated to next a0-a23 output t rae x 24.6 ns 9 wr or hwr width low t ww x (1 + w) ? 3.2 46 ns 10 wr or hwr asserted to d0-d15 valid t do ? 1 ns 11 d0-d15 valid to wr or hwr negated t dw x (1 + w) ? 4.2 45 ns 12 d0-d15 hold after wr or hwr negated t wd x ? 0.1 24.5 ns 13 a0-a23 valid to wait input t aw x (4 + 0.5) ? 21.7 89 ns 14 wait hold after rd , wr or hwr asserted t cw x (0.5 + 3 + n ? 2) ? 4.1 x (1.5 + 3 + n ? 2) ? 18.7 57.4 67.4 ns note: no. 1 to 12 indicate the values obtained with 1 programmed wait state. n0. 13 and 14 indicate the values obtained with 4 externally generated wait states with n = 1. ac measurement conditions: ? output levels: high = 0.8dvcc33 v/low 0.2dvcc33 v, cl = 30 pf ? input levels: high = 0.7dvcc33 v/low 0.3dvcc33 v w: number of wait state cycles inserted (0 to 7 for programmed wait insertion) n: value of n for (3 + n) wait insertion
TMP1962F10AXBG 2006-02-21 tmp1962f-88 (2) dvcc2m = fvcc2 = cvcc2 = 2.5 v 0.2 v, fvcc3 = 3.3 v 0.3 v, avcc3m = 3.3 0.2 v, dvcc33 = 2.5 v 0.2 v, ta = -20 to 85 c (m = 1 to 2) 1. syscr3 = 0, 1 programmed wait state equation 40.5 mhz (fsys) (note) no. parameter symbol min max min max unit 1 system clock period (x) t sys 24.6 ns 2 a0-a23 valid to rd , wr or hwr asserted t ac x ? 5.1 19.5 ns 3 a0-a23 hold after rd , wr or hwr negated t car x ? 1.6 23 ns 4 a16-a23 valid to d0-d15 data in t ad x (2 + w) ? 36.8 37 ns 5 rd asserted to d0-d15 data in t rd x (1 + w) ? 31.7 17.5 ns 6 rd width low t rr x (1 + w) ? 2.2 47 ns 7 d0-d15 hold after rd negated t hr 0 0 ns 8 rd negated to next a0-a23 output t rae x ? 0.1 24.5 ns 9 wr or hwr width low t ww x (1 + w) ? 2.7 46.5 ns 10 wr or hwr asserted to d0-d15 valid t do ? 1.5 ns 11 d0-d15 valid to wr or hwr negated t dw x (1 + w) ? 3.8 45.5 ns 12 d0-d15 hold after wr or hwr negated t wd x ?0.1 24.5 ns 13 a0-a23 valid to wait input t aw x (3 + 0.5) ? 22.6 63.5 ns 14 wait hold after rd , wr or hwr asserted t cw x (0.5 + 3 + n ? 2) ? 5.1 x (1.5 + 3 + n ? 2) ? 19.7 56.4 66.4 ns note: no. 1 to 12 indicate the values obtained with 1 programmed wait state. n0. 13 and 14 indicate the values obtained with 4 externally generated wait states with n = 1. ac measurement conditions: ? output levels: high = 0.8dvcc33 v/low 0.2dvcc33 v, cl = 30 pf ? input levels: high = 0.7dvcc33 v/low 0.3dvcc33 v w: number of wait state cycles inserted (0 to 7 for programmed wait insertion) n: value of n for (3 + n) wait insertion
TMP1962F10AXBG 2006-02-21 tmp1962f-89 2. syscr3 = 1, 1 programmed wait state equation 40.5 mhz (fsys) (note) no. parameter symbol min max min max unit 1 system clock period (x) t sys 24.6 ns 2 a0-a23 valid to rd , wr or hwr asserted t ac 2x ? 5.2 44 ns 3 a0-a23 hold after rd , wr or hwr negated t car x ? 1.6 23 ns 4 a16-a23 valid to d0-d15 data in t ad x (3 + w) ? 36.9 61.5 ns 5 rd asserted to d0-d15 data in t rd x (1 + w) ? 31.7 17.5 ns 6 rd width low t rr x (1 + w) ? 2.2 47 ns 7 d0-d15 hold after rd negated t hr 0 0 ns 8 rd negated to next a0-a23 output t rae x ? 0.1 24.5 ns 9 wr or hwr width low t ww x (1 + w) ? 2.7 46.5 ns 10 wr or hwr asserted to d0-d15 valid t do ? 1.5 ns 11 d0-d15 valid to wr or hwr negated t dw x (1 + w) ? 3.8 45.5 ns 12 d0-d15 hold after wr or hwr negated t wd x ?0.1 24.5 ns 13 a0-a23 valid to wait input t aw x (4 + 0.5) ? 22.6 88.1 ns 14 wait hold after rd , wr or hwr asserted t cw x (0.5 + 3 + n ? 2) ? 5.1 x (1.5 + 3 + n ? 2) ? 19.7 56.4 66.4 ns note: no. 1 to 12 indicate the values obtained with 1 programmed wait state. n0. 13 and 14 indicate the values obtained with 4 externally g enerated wait states with n = 1. ac measurement conditions: ? output levels: high = 0.8dvcc33 v/low 0.2dvcc33 v, cl = 30 pf ? input levels: high = 0.7dvcc33 v/low 0.3dvcc33 v w: number of wait state cycles inserted (0 to 7 for programmed wait insertion) n: value of n for (3 + n) wait insertion
TMP1962F10AXBG 2006-02-21 tmp1962f-90 (3) dvcc2m = fvcc2 = cvcc2 = 2.5 v 0.2 v, fvcc3 = 3.3 v 0.3 v, avcc3m = 3.3 0.2 v, dvcc33 = 1.8 v 0.15 v, ta = -20 to 85 c (m = 1 to 2) 1. syscr3 = 0, 2 programmed wait states equation 40.5 mhz (fsys) (note) no. parameter symbol min max min max unit 1 system clock period (x) t sys 24.6 ns 2 a0-a23 valid to rd , wr or hwr asserted t ac x ? 5.1 19.5 ns 3 a0-a23 hold after rd , wr or hwr negated t car x ? 1.6 23 ns 4 a0-a23 valid to d0-d15 data in t ad x (2 + w) ? 42.4 56 ns 5 rd asserted to d0-d15 data in t rd x (1 + w) ? 37.3 36.5 ns 6 rd width low t rr x (1 + w) ? 2.3 71.5 ns 7 d0-d15 hold after rd negated t hr 0 0 ns 8 rd negated to next a0-a23 output t rae x ? 0.1 24.5 ns 9 wr or hwr width low t ww x (1 + w) ? 2.8 71 ns 10 wr or hwr asserted to d0-d15 valid t do ? 2 ns 11 d0-d15 valid to wr or hwr negated t dw x (1 + w) ? 3.8 70 ns 12 d0-d15 hold after wr or hwr negated t wd x ? 0.1 24.5 ns 13 a0-a23 valid to wait input t awh x (3 + 0.5) ? 28.1 58 ns 14 wait hold after rd , wr or hwr asserted t cw x (0.5 + 3 + n ? 2) ? 6.1 x (1.5 + 3 + n ? 2) ? 24.7 55.4 61.4 ns note: no. 1 to 12 indicate the values obtained with 1 programmed wait state. n0. 13 and 14 indicate the values obtained with 4 externally generated wait states with n = 1. ac measurement conditions: ? output levels: high = 0.8dvcc33 v/low 0.2dvcc33 v, cl = 30 pf ? input levels: high = 0.7dvcc33 v/low 0.3dvcc33 v w: number of wait state cycles inserted (0 to 7 for programmed wait insertion) n: value of n for (3 + n) wait insertion
TMP1962F10AXBG 2006-02-21 tmp1962f-91 2. syscr3 = 1, 2 programmed states equation 40.5 mhz (fsys) (note) no. parameter symbol min max min max unit 1 system clock period (x) t sys 24.6 ns 2 a0-a23 valid to rd , wr or hwr asserted t ac 2x ? 5.2 44 ns 3 a0-a23 hold after rd , wr or hwr negated t car x ? 1.6 23 ns 4 a16-a23 valid to d0-d15 data in t ad x (3 + w) ? 42.5 80.5 ns 5 rd asserted to d0-d15 data in t rd x (1 + w) ? 37.3 36.5 ns 6 rd width low t rr x (1 + w) ? 2.3 71.5 ns 7 d0-d15 hold after rd negated t hr 0 0 ns 8 rd negated to next a0-a23 output t rae x ? 0.1 24.5 ns 9 wr or hwr width low t ww x (1 + w) ? 2.8 71 ns 10 wr or hwr asserted to d0-d15 valid t do ? 2 ns 11 d0-d15 valid to wr or hwr negated t dw x (1 + w) ? 3.8 70 ns 12 d0-d15 hold after wr or hwr negated t wd x ? 0.1 24.5 ns 13 a0-a23 valid to wait input t awh x (4 + 0.5) ? 28.1 82.6 ns 14 wait hold after rd , wr or hwr asserted t cw x (0.5 + 3 + n ? 2) ? 6.1 x (1.5 + 3 + n ? 2) ? 24.7 55.4 61.4 ns note: no. 1 to 12 indicate the values obtained with 1 programmed wait state. n0. 13 and 14 indicate the values obtained with 4 externally generated wait states with n = 1. ac measurement conditions: ? output levels: high = 0.8dvcc33 v/low 0.2dvcc33 v, cl = 30 pf ? input levels: high = 0.7dvcc33 v/low 0.3dvcc33 v w: number of wait state cycles inserted (0 to 7 for programmed wait insertion) n: value of n for (3 + n) wait insertion
TMP1962F10AXBG 2006-02-21 tmp1962f-92 (1) read cycle timing (syscr3 = 0, 1 programmed wait state) t car t rr t hr t ad internal clk rd t ac t rd a 0 to a23 bus cycle = 4 clk cycles s1 s2 s3 s1 w1 d0 to d15 d0 to d15 t rae 0 cs to 3 cs w / r
TMP1962F10AXBG 2006-02-21 tmp1962f-93 (2) read cycle timing (syscr3 = 1, 1 programmed wait state) t car t rr t hr t ad t ad internal clk rd s0 s1 s2 s3 s0 d0 to d15 d0 to d15 t ac t rd a 16 to a 23 bus cycle = 5 clk cycles w1 t rae 0 cs to 3 cs w / r
TMP1962F10AXBG 2006-02-21 tmp1962f-94 (3) read cycle timing syscr3 = 1, 2 externally generated wait states with n = 1) t aw internal clk rd a 0 to a23 bus cycle = 6 clk cycles wait d0 to d15 d0 to d15 s1 w s2 s3 s0 w t cw 0 cs to 3 cs w / r
TMP1962F10AXBG 2006-02-21 tmp1962f-95 (4) read cycle timing (syscr3 = 1, 4 externally generated wait states with n = 1) t aw internal clk rd a 0 to a23 bus cycle = 8 clk cycles wait d0 to d15 d0 to d15 s1 s2 s3 s0 w t cw 0 cs to 3 cs w / r w w w
TMP1962F10AXBG 2006-02-21 tmp1962f-96 (5) write cycle timing (syscr3 = 1, zero wait sate) t ww t car t dw internal clk wr , hwr 0 cs to 3 cs w / r t ac a 0 to a23 bus cycle = 4 clk cycles t wd d0 to d15 d0 to d15 t do
TMP1962F10AXBG 2006-02-21 tmp1962f-97 4.8 transfer with dma request the following shows an example of a transfer between the on-chip ram and an external device in multiplex bus mode. ? 16-bit data bus width, non-recovery time ? level data transfer mode ? transfer size of 16 bits, device port size (dps) of 16 bits ? source/destination: on-chip ram/external device the following shows transfer operation timing of the on-chip ram to an external bus during write operation (memory-to-memory transfer). dreqn a le a [23:16] a d [15:0] rd wr hwr csn w / r (n - 2)th transfer (n - 1)th transfer nth transfer (1) (2) (1) indicates the condition under which nth transfer is performed successfully. (2) indicates the condi tion under which (n + 1)th transfer is not performed.
TMP1962F10AXBG 2006-02-21 tmp1962f-98 (1) dvcc2m = fvcc2 = cvcc2 = 2.5 v 0.2 v, fvcc3 = 3.3 v 0.3 v, avcc3m = 3.3 0.2 v, dvcc33 = 2.3 v to 3.3 v, ta = -20 to 85 c (m = 1 to 2) equation 40.5 mhz (fsys) (note) no. parameter symbol (1) min (2) max min max unit 2 rd asserted to dreqn negated (external device to on-chip ram transfer) tdreq_r wx ? 4.2 (2w + ale + 6) x ? 51 45 195 ns 3 wr / hwr rising to dreqn negated (on-chip ram to external device transfer) tdreq_w 0 (2w + ale + 4) x ? 51.8 0 145 ns (2) dvcc2m = fvcc2 = cvcc2 = 2.5 v 0.2 v, fvcc3 = 3.3 v 0.3 v, avcc3m = 3.3 0.2 v, dvcc33 = 1.8 v 0.15 v, ta = 20 to 85 c (m = 1 to 2) equation 40.5 mhz (fsys) (note) no. parameter symbol (1) min (2) max min max unit 2 rd asserted to dreqn negated (external device to on-chip ram transfer) tdreq_r wx ? 6.2 (2w + ale + 6) x ? 56 43 190 ns 3 wr / hwr rising to dreqn negated (on-chip ram to external device transfer) tdreq_w 0 (2w + ale + 4) x ? 56.8 0 140 ns w: number of wait-state cycles inserted. in the case of (1 + n) externally generated wait states with n = 1, w becomes 2. ale: apply ale = 0 for ale 0.5 clock, ale = 1 for ale 1.5 clock. the values in the above table are obtained with w = 2, ale = 0.
TMP1962F10AXBG 2006-02-21 tmp1962f-99 4.9 serial channel timing (1) i/o interface mode (dvcc3n = 3.0 v 0.3v) in the table below, the letter x represents the fsys cycle period, which varies depending on the programming of the clock gear function. 1. sclk input mode (sio0 to sio6) equation 40.5 mhz parameter symbol min max min max unit sclk period t scy 12x 296 ns txd data to sclk rise or fall * t oss 2x ? 45 4 ns txd data hold after sclk rise or fall * t ohs 8x ? 15 182 ns rxd data valid to sclk rise or fall * t srd 30 30 ns rxd data hold after sclk rise or fall * t hsr 2x ? 30 19 ns * sclk rise or fall: measured relative to the programmed active edge of sclk. 2. sclk output mode (sio0 to sio6) equation 40.5 mhz parameter symbol min max min max unit sclk period (programmable) t scy 8x 197 ns txd data to sclk rise t oss 4x ? 10 88 ns txd data hold after sclk rise t ohs 4x ? 10 88 ns rxd data valid to sclk rise t srd 45 45 ns rxd data hold after sclk rise t hsr 0 0 ns
TMP1962F10AXBG 2006-02-21 tmp1962f-100 (2) i/o interface mode (dvcc3n = 2.5 v 0.2 v) in the table below, the letter x represents the fsys cycle period, which varies depending on the programming of the clock gear function. 1. sclk input mode (sio0 to sio6) equation 40.5 mhz parameter symbol min max min max unit sclk period t scy 16x 395 ns txd data to sclk rise or fall * t oss 4x ? 60 38 ns txd data hold after sclk rise or fall * t ohs 10x ? 15 232 ns rxd data valid to sclk rise or fall * t srd 30 30 ns rxd data hold after sclk rise or fall * t hsr 2x + 10 59 ns * sclk rise or fall: measured relative to the programmed active edge of sclk. 2. sclk output mode (sio0 to sio6) equation 40.5 mhz parameter symbol min max min max unit sclk period (programmable) t scy 8x 197 ns txd data to sclk rise t oss 4x ? 10 88 ns txd data hold after sclk rise t ohs 4x ? 10 88 ns rxd data valid to sclk rise t srd 60 60 ns rxd data hold after sclk rise t hsr 0 0 ns output data txd input data rxd sclk sck output mode/ active-high scl input mode 0 valid t oss t ohs 12 3 t srd t hsr 0 1 23 valid valid valid sclk active-low sck in p ut mode t scy
TMP1962F10AXBG 2006-02-21 tmp1962f-101 4.10 sbi timing (1) i2c mode in the table below, the letters x and t represent the fsys and t0 cycle periods, respectively. the letter n denotes the value of n programmed into the sck[2:0] (scl output frequency select) field in the sbi0cr1. equation standard mode f sys = 8 mhz n = 4 fast mode f sys = 32 mhz n = 4 parameter symbol min max min max min max unit scl clock frequency t scl 0 0 100 0 400 khz hold time for start condition t hd:sta 4.0 0.6 s scl clock low width (input) (note 1) t low 4.7 1.3 s scl clock high width (output) (note 2) t high 4.0 0.6 s setup time for a repeated start condition t su:sta (note 5) 4.7 0.6 s data hold time (input) (note 3, 4) t hd:dat 0.0 0.0 s data setup time t su:dat 250 100 ns setup time for stop condition t su:sto 4.0 0.6 s bus free time between stop and start conditions t buf (note 5) 4.7 1.3 s note 1: scl clock low width (output) is calculated with (2 (n ? 1) + 4) t. standard mode: 6 sec ? typ (fsys = 8 mhz, n = 4) fast mode: 1.5 sec ? typ (fsys = 32 mhz, n = 4) note 2: scl clock high width (output) is calculated with (2 (n ? 1)) t. standard mode: 4 sec ? typ (fsys = 8mhz, n = 4) fast mode: 1 sec ? typ (fsys = 32 mhz, n = 4) note 3: the output data hold time is equal to 12x. note 4: the philips i 2 c-bus specification states that a device must internally provide a hold time of at least 300 ns for the sda signal to bridge the undefi ned region of the fall edge of scl. however, TMP1962F10AXBG sbi does not satisfy this requirem ent. also, the output buffer for scl does not incorporate slope control of the falling edges; theref ore, the equipment manufacturer should design so that the input data hold time shown in the table is satisfied, including tr/tf of the scl and sda lines. note 5: software-dependent sda scl t low t hd;sta t scl t high t r t su;dat t hd;dat t su;sta t su;sto t buf s: start condition sr: repeated start condition p: stop condition t f ssrp note 6: to operate the sbi in i 2 c fast mode, the fysy frequency must be no less than 20 mhz. to operate the sbi in i 2 c standard mode, the fsys frequency must be no less than 4 mhz.
TMP1962F10AXBG 2006-02-21 tmp1962f-102 (2) clock-synchronous 8-bit sio mode in the table below, the letters x and t represent the fsys and t0 cycle periods, respectively. the letter n denotes the value of n programmed into the sck[2:0] (scl output frequency select) field in the sbi0cr1. the electrical specifications below are for an sck signal with a 50% duty cycle. 1. sck input mode equation 40.5 mhz parameter symbol min max min max unit sck period t scy 16x 395 ns so data to sck rise t oss (t scy /2) ? (6x + 30) 19 ns so data hold after sck rise t ohs (t scy /2) + 4x 296 ns si data valid to sck rise t srd 0 0 ns si data hold after sck rise t hsr 4x + 10 108 ns 2. sck output mode equation 32 mhz parameter symbol min max min max unit sck period (programmable) t scy 2 n ? t 1000 ns so data to sck rise t oss (t scy /2) ? 20 480 ns so data hold after sck rise t ohs (t scy /2) ? 20 480 ns si data valid to sck rise t srd 2x + 30 92 ns si data hold after sck rise t hsr 0 0 ns output data txd input data txd sclk 0 valid t oss t scy t ohs 1 2 3 t srd t hsr 0 1 2 3 valid valid valid
TMP1962F10AXBG 2006-02-21 tmp1962f-103 4.11 event counter in the table below, the letter x re presents the fsys cycle period. equation 40.5 mhz parameter symbol min max min max unit clock low pulse width t vckl 2x + 100 149 ns clock high pulse width t vckh 2x + 100 149 ns 4.12 timer capture in the table below, the letter x re presents the fsys cycle period. equation 40.5 mhz parameter symbol min max min max unit low pulse width t cpl 2x + 100 149 ns high pulse width t cph 2x + 100 149 ns 4.13 general interrupts in the table below, the letter x re presents the fsys cycle period. equation 40.5 mhz parameter symbol min max min max unit low pulse width for int0-inta t intal x + 100 125 ns high pulse width for int0-inta t intah x + 100 125 ns 4.14 nmi and stop wake-up interrupts equation 40.5 mhz parameter symbol min max min max unit low pulse width for nmi and int0-int4 t intbl 100 100 ns high pulse width for int0-int4 t intbh 100 100 ns 4.15 scout pin equation 40.5 mhz parameter symbol min max min max unit clock high pulse width t sch 0.5t ? 5 7.4 ns clock low pulse width t scl 0.5t ? 5 7.4 ns note: in the above table, the letter t represent s the cycle period of t he scout output clock. t sch t scl scout
TMP1962F10AXBG 2006-02-21 tmp1962f-104 4.16 bus request and bus acknowledge signals t aba (note 1) busrq a le a 0 to a23, rd , wr busak cs0 to cs3 , w / r , hwr a d0 to ad15 t baa (note 2) (note 2) equation 40.5 mhz parameter symbol min max min max unit bus float to busak asserted t aba 0 80 0 80 ns bus float after busak negated t baa 0 80 0 80 ns note 1: if the current bus cycle has not te rminated due to wait-state insertion, the TMP1962F10AXBG does not respond to busrq until the wait state ends. note 2: this broken line indicates that output buffers are disabled, not that the signals are at indeterminate states. the pin holds the last logic value present at that pin before the bus is relinquished. this is dynamically accomplished through external load capacitances. the equipment manufacturer may maintain the bus at a predefined state by means of off-chip restores, but he or she should design, considering the time (determined by the cr constant) it takes for a signal to reach a desired state. the on-chip, integrated programmable pullup/pulldown resistors remain active, depending on internal signal states.
TMP1962F10AXBG 2006-02-21 tmp1962f-105 4.17 kwup input pull-up register active equation 40.5 mhz parameter symbol min max min max unit low pulse width for key0-d tky tbl 100 100 ns high pulse width for key0-d tky tbh 100 100 ns pull-up register inactive equation 40.5 mhz parameter symbol min max min max unit low pulse width for key0-d tky tbl 100 100 ns 4.18 dual pulse input equation 40.5mhz parameter symbol min max min max unit dual input pulse period tdcyc 8y 395 ns dual input pulse setup tabs y + 20 70 ns dual input pulse hold tabh y + 20 70 ns y: sampling clock (fsys/2) 4.19 adtrg input equation 40.5 mhz parameter symbol min max min max unit adrg low level pulse width tad l fsysy/2 + 20 32.4 ns adtrg high level pulse interval tadh fsysy/2 + 20 32.4 ns tabs tabh tdcyc b a
TMP1962F10AXBG 2006-02-21 tmp1962f-106 5. others esd mm ? 200v hbm ? 1200v
TMP1962F10AXBG tmp1962f-107 6.package p-fbga281-1313-0.65b6

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